Patents by Inventor Myung jin Yim

Myung jin Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11926807
    Abstract: A cleaning composition for removing post-etch or post-ash residues from a semiconductor substrate, and a cleaning method using the same are disclosed. The cleaning composition can comprise water; a fluorine compound; an alkanolamine compound; and a corrosion inhibitor. The corrosion inhibitor is a mixture of a first corrosion inhibitor and a second corrosion inhibitor. When using the cleaning composition, it is possible to efficiently remove the residues of various aspects existing on a surface of the substrate or the semiconductor device without damage to a substrate or a semiconductor device including various metal layers, insulating layers, etc. Accordingly, when a highly integrated and miniaturized semiconductor device is manufactured, it may be advantageously applied to the removal of residues generated on the surface of the substrate or the semiconductor device.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: March 12, 2024
    Assignee: ENF TECHNOLOGY CO., LTD.
    Inventors: Jun Her, Na Rae Yim, Hyun Jin Jung, Myung Ho Lee, Myung Geun Song
  • Publication number: 20230091428
    Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 23, 2023
    Inventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
  • Patent number: 11531174
    Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
  • Publication number: 20210405306
    Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Vivek RAGHUNATHAN, Myung Jin YIM
  • Patent number: 11156788
    Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Vivek Raghunathan, Myung Jin Yim
  • Patent number: 10953593
    Abstract: Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound are disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than about 10 microns. Other apparatuses and methods are disclosed.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Myung Jin Yim, Jason M. Brand
  • Patent number: 10727368
    Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Myung Jin Yim, Seungjae Lee, Sandeep Razdan
  • Publication number: 20200200987
    Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 25, 2020
    Inventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
  • Publication number: 20190324223
    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a mold material, wherein a plurality of die are embedded in the mold material, a package substrate, wherein the mold material comprising the plurality of die is at least partially embedded in a cavity of the substrate, and wherein a liner is between side and bottom portions of the mold material and the package substrate, at least one optical die disposed on the package substrate, and a thermal solution disposed on a top surface of the optical die.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Myung Jin Yim, Sang Yup Kim
  • Publication number: 20190302379
    Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.
    Type: Application
    Filed: July 14, 2016
    Publication date: October 3, 2019
    Inventors: Vivek RAGHUNATHAN, Myung Jin YIM
  • Patent number: 10347615
    Abstract: Some forms include an electronic package that includes a photo-detecting receiver IC and a receiver IC. The electronic package includes a mold that encloses the photo-detecting receiver IC and the receiver IC. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching one another. Other forms include an optical module that includes a substrate and an electronic package mounted on the substrate. The electronic package includes a photo-detecting receiver IC and a receiver IC that are enclosed within a mold. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching. Other forms include a method that includes forming a mold that includes a photo-detecting receiver IC and a receiver IC that are adjacent to one another without touching. The photo-detecting receiver IC includes optical components that are exposed on a surface of the mold.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Myung Jin Yim, Jay S. Lee, Jong-Min Hong
  • Publication number: 20190172821
    Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die, and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 6, 2019
    Applicant: Intel Corporation
    Inventor: Myung Jin Yim
  • Patent number: 10242976
    Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die. and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventor: Myung Jin Yim
  • Publication number: 20190006549
    Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 3, 2019
    Inventors: Myung Jin YIM, Seungjae LEE, Sandeep RAZDAN
  • Publication number: 20180348434
    Abstract: Embodiments herein may include apparatuses, systems, and processes related to a photonic die package with an edge lens that includes a photonic integrated circuit (IC) die, a lens coupled to the photonic IC die and disposed at an edge of the package to provide an optical path at the edge of the package for photon signals generated or received by the photonic IC die, and an electronic IC die coupled to the photonic IC die, where the electronic IC die is to process electrical signals received from the photonic IC die, and where the electronic IC die and the photonic IC die are in a stack formation to facilitate thermal energy conduction from the electronic IC die to the photonic IC die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Myung Jin Yim, Sang Yup Kim, Woosung Kim
  • Publication number: 20180229421
    Abstract: A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Inventors: Myung Jin Yim, Jason M. Brand
  • Publication number: 20180188448
    Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die. and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.
    Type: Application
    Filed: December 31, 2016
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventor: Myung Jin Yim
  • Patent number: 10014654
    Abstract: Optoelectronic packaging assemblies are provided that are useful for optical data, transfer In high performance computing applications, board to board in data centers, memory to CPU, switch/FPGA (field programmable gate array) for chip to chip interconnects, and memory extension. The packaging assemblies provide fine pitch flip chip interconnects and chip stacking assemblies with good thermo-mechanical reliability. Underfill dams and optical overhang regions and are provided for optical interconnection.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Myung Jin Yim, Ansheng Liu, Valentin Yepanechnikov
  • Patent number: 9950464
    Abstract: Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound is disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than about 10 microns. Other apparatuses and methods are disclosed.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Myung Jin Yim, Jason M. Brand
  • Patent number: 9900102
    Abstract: Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, the apparatus may include an optical transceiver with an opto-electronic component disposed in a first portion of a die, and a trace coupled with the opto-electronic component and disposed to extend to a surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration. The apparatus may include a second trace disposed in the second portion of the die to extend to the surface in the second portion, to provide electrical connection for the other integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Olufemi I. Dosunmu, Myung Jin Yim, Ansheng Liu