Patents by Inventor Myung jin Yim
Myung jin Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12078853Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.Type: GrantFiled: September 14, 2021Date of Patent: September 3, 2024Assignee: Intel CorporationInventors: Vivek Raghunathan, Myung Jin Yim
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Publication number: 20240264396Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.Type: ApplicationFiled: April 2, 2024Publication date: August 8, 2024Applicant: Intel CorporationInventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
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Patent number: 11982854Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.Type: GrantFiled: November 22, 2022Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
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Publication number: 20230091428Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.Type: ApplicationFiled: November 22, 2022Publication date: March 23, 2023Inventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
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Patent number: 11531174Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.Type: GrantFiled: September 28, 2017Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
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Publication number: 20210405306Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Applicant: Intel CorporationInventors: Vivek RAGHUNATHAN, Myung Jin YIM
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Patent number: 11156788Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.Type: GrantFiled: July 14, 2016Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Vivek Raghunathan, Myung Jin Yim
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Patent number: 10953593Abstract: Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound are disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than about 10 microns. Other apparatuses and methods are disclosed.Type: GrantFiled: April 16, 2018Date of Patent: March 23, 2021Assignee: Micron Technology, Inc.Inventors: Myung Jin Yim, Jason M. Brand
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Patent number: 10727368Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.Type: GrantFiled: April 1, 2016Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Myung Jin Yim, Seungjae Lee, Sandeep Razdan
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Publication number: 20200200987Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.Type: ApplicationFiled: September 28, 2017Publication date: June 25, 2020Inventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
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Publication number: 20190324223Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a mold material, wherein a plurality of die are embedded in the mold material, a package substrate, wherein the mold material comprising the plurality of die is at least partially embedded in a cavity of the substrate, and wherein a liner is between side and bottom portions of the mold material and the package substrate, at least one optical die disposed on the package substrate, and a thermal solution disposed on a top surface of the optical die.Type: ApplicationFiled: December 29, 2016Publication date: October 24, 2019Applicant: Intel CorporationInventors: Myung Jin Yim, Sang Yup Kim
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Publication number: 20190302379Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.Type: ApplicationFiled: July 14, 2016Publication date: October 3, 2019Inventors: Vivek RAGHUNATHAN, Myung Jin YIM
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Patent number: 10347615Abstract: Some forms include an electronic package that includes a photo-detecting receiver IC and a receiver IC. The electronic package includes a mold that encloses the photo-detecting receiver IC and the receiver IC. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching one another. Other forms include an optical module that includes a substrate and an electronic package mounted on the substrate. The electronic package includes a photo-detecting receiver IC and a receiver IC that are enclosed within a mold. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching. Other forms include a method that includes forming a mold that includes a photo-detecting receiver IC and a receiver IC that are adjacent to one another without touching. The photo-detecting receiver IC includes optical components that are exposed on a surface of the mold.Type: GrantFiled: March 24, 2015Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Myung Jin Yim, Jay S. Lee, Jong-Min Hong
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Publication number: 20190172821Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die, and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.Type: ApplicationFiled: February 4, 2019Publication date: June 6, 2019Applicant: Intel CorporationInventor: Myung Jin Yim
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Patent number: 10242976Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die. and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.Type: GrantFiled: December 31, 2016Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventor: Myung Jin Yim
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Publication number: 20190006549Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.Type: ApplicationFiled: April 1, 2016Publication date: January 3, 2019Inventors: Myung Jin YIM, Seungjae LEE, Sandeep RAZDAN
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Publication number: 20180348434Abstract: Embodiments herein may include apparatuses, systems, and processes related to a photonic die package with an edge lens that includes a photonic integrated circuit (IC) die, a lens coupled to the photonic IC die and disposed at an edge of the package to provide an optical path at the edge of the package for photon signals generated or received by the photonic IC die, and an electronic IC die coupled to the photonic IC die, where the electronic IC die is to process electrical signals received from the photonic IC die, and where the electronic IC die and the photonic IC die are in a stack formation to facilitate thermal energy conduction from the electronic IC die to the photonic IC die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Myung Jin Yim, Sang Yup Kim, Woosung Kim
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Publication number: 20180229421Abstract: A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Inventors: Myung Jin Yim, Jason M. Brand
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Publication number: 20180188448Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die. and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.Type: ApplicationFiled: December 31, 2016Publication date: July 5, 2018Applicant: Intel CorporationInventor: Myung Jin Yim
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Patent number: 10014654Abstract: Optoelectronic packaging assemblies are provided that are useful for optical data, transfer In high performance computing applications, board to board in data centers, memory to CPU, switch/FPGA (field programmable gate array) for chip to chip interconnects, and memory extension. The packaging assemblies provide fine pitch flip chip interconnects and chip stacking assemblies with good thermo-mechanical reliability. Underfill dams and optical overhang regions and are provided for optical interconnection.Type: GrantFiled: December 27, 2013Date of Patent: July 3, 2018Assignee: Intel CorporationInventors: Myung Jin Yim, Ansheng Liu, Valentin Yepanechnikov