Patents by Inventor Myung-Jo Chun
Myung-Jo Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10522430Abstract: A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.Type: GrantFiled: April 27, 2017Date of Patent: December 31, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Zhan Zhan, Hwa Sung Rhee, Myung Jo Chun
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Publication number: 20180012814Abstract: A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.Type: ApplicationFiled: April 27, 2017Publication date: January 11, 2018Inventors: Zhan ZHAN, Hwa Sung RHEE, Myung Jo CHUN
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Patent number: 8111553Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.Type: GrantFiled: April 16, 2010Date of Patent: February 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Young Seo, Hee-Seog Jeon, Kwang-Tae Kim, Ji-Hoon Park, Myung-Jo Chun
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Patent number: 8053342Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.Type: GrantFiled: July 14, 2010Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young-Ho Kim, Myung-Jo Chun, Jung-Ho Moon
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Publication number: 20100285641Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.Type: ApplicationFiled: July 14, 2010Publication date: November 11, 2010Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young-Ho Kim, Myung-Jo Chun, Jung-Ho Moon
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Publication number: 20100265765Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.Type: ApplicationFiled: April 16, 2010Publication date: October 21, 2010Inventors: Bo-Young Seo, Hee-Seog Jeon, Kwang-Tae Kim, Ji-Hoon Park, Myung-Jo Chun
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Patent number: 7777256Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.Type: GrantFiled: June 3, 2008Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young-Ho Kim, Myung-Jo Chun, Jung-Ho Moon
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Publication number: 20100167487Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Inventors: Myung-Jo Chun, Hee-Seong Jeon, Yong-Kyu Lee, Young-Ho Kim
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Patent number: 7733696Abstract: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.Type: GrantFiled: June 13, 2007Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Kyu Lee, Myung-Jo Chun, Young-Ho Kim, Hee-Seog Jeon, Jeong-Uk Han
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Publication number: 20100059888Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.Type: ApplicationFiled: November 9, 2009Publication date: March 11, 2010Inventors: Yong-Kyu Lee, Hee-Seog JEON, Jeong-Uk HAN, Young-Ho Kim, Myung-Jo Chun
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Patent number: 7659573Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.Type: GrantFiled: August 2, 2007Date of Patent: February 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ho Kim, Yong-kyu Lee, Myung-jo Chun
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Patent number: 7638387Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.Type: GrantFiled: June 27, 2007Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Kyu Lee, Hee-Seog Jeon, Jeong-Uk Han, Young-Ho Kim, Myung-Jo Chun
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Publication number: 20080308875Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.Type: ApplicationFiled: June 3, 2008Publication date: December 18, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Kyu LEE, Jeong-Uk HAN, Hee-Seog JEON, Young-Ho KIM, Myung-Jo CHUN, Jung-Ho MOON
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Publication number: 20080179692Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.Type: ApplicationFiled: January 14, 2008Publication date: July 31, 2008Inventors: Myung-Jo Chun, Hee-Seog Jeon, Yong-Kyu Lee, Young-Ho Kim
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Publication number: 20080093646Abstract: A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the channel region to at least partially overlap the drain region, and a spacer arranged at each of both side walls of the gate structure. A threshold voltage value of the offset region changes depending on a dielectric constant of the spacer.Type: ApplicationFiled: November 20, 2006Publication date: April 24, 2008Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young Ho Kim, Myung-Jo Chun
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Publication number: 20080080244Abstract: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.Type: ApplicationFiled: June 13, 2007Publication date: April 3, 2008Inventors: Yong-Kyu Lee, Myung-Jo Chun, Young-Ho Kim, Hee-Seog Jeon, Jeong-Uk Han
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Publication number: 20080035962Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.Type: ApplicationFiled: August 2, 2007Publication date: February 14, 2008Inventors: Young-ho Kim, Yong-kyu Lee, Myung-jo Chun
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Publication number: 20080003810Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.Type: ApplicationFiled: June 27, 2007Publication date: January 3, 2008Inventors: Yong-Kyu Lee, Hee-Seog Jeon, Jeong-Uk Han, Young-Ho Kim, Myung-Jo Chun