Abstract: A “multiple return-to-zero” (MRZ) current switching DAC. In operation, the outputs of respective current sources are selectively directed to respective intermediate nodes in response to respective control signals which vary with a digital input word, and in synchronization with a clock CK1. A plurality of MRZ current switches are connected between respective intermediate nodes and the DAC's analog output. The MRZ switches are driven with a clock CK2 which toggles in synchronization with CK1 at a frequency fCK2=N*fCK1. The MRZ switches are operated such that switching noise that arises when CK1 is asserted is prevented from appearing on the analog output. When properly arranged, the DAC can generate a direct digital waveform at RF frequencies, with N chosen to produce an output spectrum such that the DAC's output power is relatively high within the desired frequency range.

Abstract: The present invention relates generally to a digital-to-analog converter (DAC) calibration. The present invention may be implemented by a DAC calibration system including a first current source, a first switch coupled to the first current source, a second current source, a second switch coupled to the second current source, an output node coupled to the first switch and the second switch, a first calibration module coupled to the output node, an average current measurement module coupled to the first calibration module, and a second calibration module coupled to the average current measurement module.

Abstract: The present invention relates generally to a digital-to-analog converter (DAC) calibration. The present invention may be implemented by a DAC calibration system including a first current source, a first switch coupled to the first current source, a second current source, a second switch coupled to the second current source, an output node coupled to the first switch and the second switch, a first calibration module coupled to the output node, an average current measurement module coupled to the first calibration module, and a second calibration module coupled to the average current measurement module.

Abstract: A hardware-efficient mapping circuit uses a base decoder to decode the control signal (the most significant bits “MSBs” of the phase angle) to provide a base value. A controller maps the control signal to a segment number to down select signed shift values from the control signal. Shifter blocks shift the data signal (the least significant bits “LSBs” of the phase angle) by the respective shift values. The shifted data signals are added/subtracted from the base value to approximate a sinusoidal amplitude for the phase angle. Down selection by a controller allows the shifter blocks to be implemented with narrow band multiplexers, which conserves both chip space and power.

Abstract: An analog-to-digital converter (ADC) uses a combination of sampling circuits and ADCs to convert the signal from analog to digital. By sampling an analog signal with a single front-end sampling circuit, the ADC substantially eliminates the dynamic error that is normally associated with mismatched parallel sampling circuits. The clean signal is then sampled a second time. Several sampling circuits arranged in parallel can be used to increase the bandwidth of the circuit. After the analog signal is sampled it is then converted to a time-interleaved digital signal. The ADC is able to achieve high-resolution broadband signal conversion while consuming much less power than other high-performance ADCs in systems such as GaAs and InP.

Abstract: A hardware-efficient mapping circuit uses a controller to down select signed shift values from the control signal (MSBs) for a particular phase angle. Shifter blocks shift the data signal (LSBs) by the respective shift values. The shifted data signals are added/subtracted from a base value decoded from the control signal to approximate a sinusoidal amplitude for the phase angle. Down selection by a controller allows the shifter blocks to be implemented with narrow band multiplexers, which conserves both chip space and power.

Abstract: A “return-to-zero” (RZ) current switching DAC includes an analog output node for which a “zero” potential has been defined. The outputs of a plurality of current sources are selectively directed to respective intermediate nodes in response to respective control signals, which are varied in synchronization with a clock signal CK. A plurality of RZ circuits are connected between respective intermediate nodes and the analog output node. In a preferred embodiment, each RZ circuit directs the current applied to a respective intermediate node to ground or to the analog output node in synchronization with CK. An output network pulls the analog output node to the “zero” potential when currents applied to the intermediate nodes are directed to ground.

Abstract: A “return-to-zero” (RZ) current switching DAC includes an analog output node for which a “zero” potential has been defined. The outputs of a plurality of current sources are selectively directed to respective intermediate nodes in response to respective control signals, which are varied in synchronization with a clock signal CK. A plurality of RZ circuits are connected between respective intermediate nodes and the analog output node. In a preferred embodiment, each RZ circuit directs the current applied to a respective intermediate node to ground or to the analog output node in synchronization with CK. An output network pulls the analog output node to the “zero” potential when currents applied to the intermediate nodes are directed to ground.

Abstract: An analog-to-digital converter includes a reference voltage generator for dividing a voltage between first and second reference voltages by a plurality of resistors serially connected therebetween and providing a plurality of reference voltages at each connecting point of the resistors; a plurality of emitter-coupled comparators for respectively generating a comparative signal by comparing the reference voltages with an analog input signal; and a plurality of constant current sources for respectively supplying an input bias current to each reference voltage input terminal of the emitter-coupled comparators.

Abstract: A voltage-to-current converter makes it possible to control conversion of a voltage to a current by considering the size of a transistor irrespective of supply voltage, input voltage, and fabrication conditions.