Patents by Inventor Myung June Lee

Myung June Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9607863
    Abstract: Integrated circuit packages with cavity are disclosed. A disclosed integrated circuit package includes a first die. A second die may be coupled to the first die by attaching the first die to a top surface of the second die. A blocking element such as a barrier structure may be formed that surrounds the second die. A cavity may be formed between the blocking element and the first die that encloses the second die. The barrier structure may help prevent underfill material from entering the cavity during underfill deposition processes. A heat spreading lid may cover the first die, second die and package substrate.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: March 28, 2017
    Assignee: Altera Corporation
    Inventor: Myung June Lee
  • Patent number: 9478491
    Abstract: Integrated circuit packages with openings surrounding a conductive via on a substrate layer are disclosed. An integrated circuit package may include a substrate layer with upper and lower surfaces. A conductive via may extend between the upper and lower surfaces of the substrate layer. The integrated circuit package further includes multiple openings in the substrate layer that may be distributed evenly in the substrate layer surrounding the conductive via. The multiple openings reduce signal insertion loss of the conductive via.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 25, 2016
    Assignee: Altera Corporation
    Inventors: Jianmin Zhang, Myung June Lee
  • Publication number: 20160240457
    Abstract: An integrated circuit package may include a first integrated circuit die attached to a front surface of a second integrated circuit die. An intermediate layer made of a molding compound is formed to surround the second integrated circuit die in a “fan-out” arrangement while leaving a surface of the second integrated circuit die exposed. Accordingly, a group of via holes is then formed in the intermediate layer and filled with a conductive material. Such a configuration forms a dual-sided stacking structure. The stacking structure may also be applicable for package-on-package packages and fan-out wafer-level chip scale packages, in which the stacking structure is formed between two heterogeneous or homogeneous integrated circuit packages.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Inventor: Myung June Lee
  • Patent number: 9330997
    Abstract: A heat spreader structure includes a planar portion and a slanted portion. The slanted portion extends at an angle from an edge of the planar portion. The first slanted portion includes a first slot. A second heat spreader structure includes a planar member, a first edge member and a second edge member. The first edge member extends only perpendicularly from a first edge of the planar member whereas the second edge member extends from the second edge of the planar member and has a slanted surface with respect to that of the planar member. In addition to that, the first and second heat spreader structure may be formed using different manufacturing methods.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 3, 2016
    Assignee: Altera Corporation
    Inventors: Ken Beng Lim, Myung June Lee, Yuan Li, Ping Chet Tan
  • Patent number: 9236341
    Abstract: A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: January 12, 2016
    Assignee: XILINIX, INC.
    Inventors: Dong W. Kim, Myung-June Lee, Suresh Ramalingam
  • Patent number: 9196575
    Abstract: Integrated circuit packages with heat dissipation function are disclosed. A disclosed integrated circuit package includes a first die attached on a top surface of a second die. The second die may be coupled to a thermally conductive block. The thermally conductive block may be embedded in a cavity formed in a package substrate. A heat spreading lid may be disposed over the package substrate. The integrated circuit package may be disposed on a printed circuit substrate via solder bumps or balls. The printed circuit substrate may have heat dissipation paths to dissipate heat from the integrated circuit package.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: November 24, 2015
    Assignee: Altera Corporation
    Inventors: Myung June Lee, Yuan Li, Yuanlin Xie