Abstract: To dynamically manage a temperature of an electronic device, a local temperature is provided by measuring a temperature of a local spot in the electronic device and a reference temperature is provided by measuring a temperature of a reference spot in the electronic device where the reference spot and the local spot are thermally coupled. A target temperature corresponding to a limit value of the reference temperature is adjusted based on the local temperature and a power level of the electronic device is controlled based on the same target temperature. The target temperature may be set to a relatively high value to secure performance of the electronic device when the local temperature is relatively low. Alternatively, the target temperature may be set to a relatively low value to pursue stability of the electronic device when the local temperature is relatively high.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: To dynamically manage a temperature of an electronic device, a local temperature is provided by measuring a temperature of a local spot in the electronic device and a reference temperature is provided by measuring a temperature of a reference spot in the electronic device where the reference spot and the local spot are thermally coupled. A target temperature corresponding to a limit value of the reference temperature is adjusted based on the local temperature and a power level of the electronic device is controlled based on the same target temperature. The target temperature may be set to a relatively high value to secure performance of the electronic device when the local temperature is relatively low. Alternatively, the target temperature may be set to a relatively low value to pursue stability of the electronic device when the local temperature is relatively high.

Abstract: To dynamically manage a temperature of an electronic device, a local temperature is provided by measuring a temperature of a local spot in the electronic device and a reference temperature is provided by measuring a temperature of a reference spot in the electronic device where the reference spot and the local spot are thermally coupled. A target temperature corresponding to a limit value of the reference temperature is adjusted based on the local temperature and a power level of the electronic device is controlled based on the same target temperature. The target temperature may be set to a relatively high value to secure performance of the electronic device when the local temperature is relatively low. Alternatively, the target temperature may be set to a relatively low value to pursue stability of the electronic device when the local temperature is relatively high.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A semiconductor device and a semiconductor system are provided. A semiconductor device includes a monitoring circuit receiving a first operating voltage and a second operating voltage, which is different from the first operating voltage, from a Power Management Integrated Circuit (PMIC) and monitoring a duration of use of a System-on-Chip (SoC) at each of the first and second operating voltages; a processing circuit calculating a normalized value based on predetermined weight information from the duration of use of the SoC at each of the first and second operating voltages; and a voltage circuit determining whether to increase an operating voltage of the SoC by comparing the normalized value with a predetermined value.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A controller configured to: acquire a temperature of a first component and a temperature of a second component; and adjust a thermal resistance of a medium between the first component and the second component based on the acquired temperature of the first component, the acquired temperature of the second component, a first temperature limit of the first component, and a second temperature limit of the second component.

Abstract: To dynamically manage a temperature of an electronic device, a local temperature is provided by measuring a temperature of a local spot in the electronic device and a reference temperature is provided by measuring a temperature of a reference spot in the electronic device where the reference spot and the local spot are thermally coupled. A target temperature corresponding to a limit value of the reference temperature is adjusted based on the local temperature and a power level of the electronic device is controlled based on the same target temperature. The target temperature may be set to a relatively high value to secure performance of the electronic device when the local temperature is relatively low. Alternatively, the target temperature may be set to a relatively low value to pursue stability of the electronic device when the local temperature is relatively high.

Abstract: A semiconductor device and a semiconductor system are provided. A semiconductor device includes a monitoring circuit receiving a first operating voltage and a second operating voltage, which is different from the first operating voltage, from a Power Management Integrated Circuit (PMIC) and monitoring a duration of use of a System-on-Chip (SoC) at each of the first and second operating voltages; a processing circuit calculating a normalized value based on predetermined weight information from the duration of use of the SoC at each of the first and second operating voltages; and a voltage circuit determining whether to increase an operating voltage of the SoC by comparing the normalized value with a predetermined value.

Abstract: A controller configured to: acquire a temperature of a first component and a temperature of a second component; and adjust a thermal resistance of a medium between the first component and the second component based on the acquired temperature of the first component, the acquired temperature of the second component, a first temperature limit of the first component, and a second temperature limit of the second component.

Abstract: A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.

Abstract: A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.

Abstract: A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.

Abstract: A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.

Abstract: In a system including a power management integrated circuit (PMIC) and a memory device, an application processor obtains control information for a memory device, the control information defining in part at least a first power supply voltage and operating clock frequency for the memory device. A memory control unit (MCU) communicates a workload indication related to queued operation commands for the memory device to a digital voltage and frequency scaling (DVFS) controller, and the DVFS controller provides a power supply voltage command to the PMIC in response to the MCU workload indication and the control information.

Abstract: A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.

Abstract: A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.

Abstract: A K way cache memory having improved operational speed and reduced power consumption is provided. The cache memory includes M cache memory units, but only activates one of the units at a given time. Moreover, only one match line is activated corresponding to a way having a tag address that matches an externally provided tag address.