Patents by Inventor Myung Kyun KWAK
Myung Kyun KWAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11087830Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.Type: GrantFiled: June 19, 2020Date of Patent: August 10, 2021Assignee: SK hynix Inc.Inventors: Myung Kyun Kwak, Min O Kim, Min Wook Oh
-
Patent number: 11049533Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.Type: GrantFiled: May 14, 2020Date of Patent: June 29, 2021Assignee: SK hynix Inc.Inventors: Min Wook Oh, Myung Kyun Kwak, Min O Kim, Chang Ki Baek
-
Publication number: 20210183417Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.Type: ApplicationFiled: May 14, 2020Publication date: June 17, 2021Applicant: SK hynix Inc.Inventors: Min Wook OH, Myung Kyun KWAK, Min O KIM, Chang Ki BAEK
-
Publication number: 20210183431Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.Type: ApplicationFiled: June 19, 2020Publication date: June 17, 2021Applicant: SK hynix Inc.Inventors: Myung Kyun KWAK, Min O KIM, Min Wook OH
-
Patent number: 10762935Abstract: A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.Type: GrantFiled: May 1, 2019Date of Patent: September 1, 2020Assignee: SK hynix Inc.Inventors: Myung Kyun Kwak, Woongrae Kim, Seung Hun Lee
-
Patent number: 10734042Abstract: A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.Type: GrantFiled: July 9, 2019Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventors: Woongrae Kim, Myung Kyun Kwak, Seung Hun Lee
-
Publication number: 20200176035Abstract: A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.Type: ApplicationFiled: July 9, 2019Publication date: June 4, 2020Applicant: SK hynix Inc.Inventors: Woongrae KIM, Myung Kyun KWAK, Seung Hun LEE
-
Publication number: 20200160896Abstract: A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.Type: ApplicationFiled: May 1, 2019Publication date: May 21, 2020Applicant: SK hynix Inc.Inventors: Myung Kyun KWAK, Woongrae KIM, Seung Hun LEE
-
Patent number: 10629248Abstract: A semiconductor device includes a bank group selection signal generation circuit and a bank group address generation circuit. The bank group selection signal generation circuit stores a bank address based on a command pulse generated to perform a read operation or a write operation. The bank group selection signal generation circuit outputs the stored bank address as a bank group selection signal. The bank group address generation circuit generates a bank group address and an internal bank group address for performing a column operation of a cell array included in a bank group selected based on the bank group selection signal.Type: GrantFiled: July 30, 2018Date of Patent: April 21, 2020Assignee: SK hynix Inc.Inventors: Woongrae Kim, Myung Kyun Kwak, Tae Yong Lee
-
Patent number: 10545822Abstract: An address processing circuit may be provided. The address processing circuit may include an address latch control circuit configured to generate a plurality of latch control signals for separately inputting/outputting a normal operation-related address signal or a data error correction operation-related address signal based on a plurality of internal command signals pertaining to a normal operation and an error correction operation. The address processing circuit may include an address latch circuit configured to latch a combined address signal for the normal operation and the error correction operation to a pipe latch according to any one of the plurality of latch control signals, and separately output the latched combined address signal for the normal operation or the data error correction operation according to the other signals of the plurality of latch control signals.Type: GrantFiled: September 28, 2017Date of Patent: January 28, 2020Assignee: SK hynix Inc.Inventor: Myung Kyun Kwak
-
Publication number: 20190279696Abstract: A semiconductor device includes a bank group selection signal generation circuit and a bank group address generation circuit. The bank group selection signal generation circuit stores a bank address based on a command pulse generated to perform a read operation or a write operation. The bank group selection signal generation circuit outputs the stored bank address as a bank group selection signal. The bank group address generation circuit generates a bank group address and an internal bank group address for performing a column operation of a cell array included in a bank group selected based on the bank group selection signal.Type: ApplicationFiled: July 30, 2018Publication date: September 12, 2019Applicant: SK hynix Inc.Inventors: Woongrae KIM, Myung Kyun KWAK, Tae Yong LEE
-
Patent number: 10134484Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.Type: GrantFiled: July 24, 2015Date of Patent: November 20, 2018Assignee: SK hynix Inc.Inventors: Myung Kyun Kwak, Bok Rim Ko
-
Publication number: 20180293132Abstract: An address processing circuit may be provided. The address processing circuit may include an address latch control circuit configured to generate a plurality of latch control signals for separately inputting/outputting a normal operation-related address signal or a data error correction operation-related address signal based on a plurality of internal command signals pertaining to a normal operation and an error correction operation. The address processing circuit may include an address latch circuit configured to latch a combined address signal for the normal operation and the error correction operation to a pipe latch according to any one of the plurality of latch control signals, and separately output the latched combined address signal for the normal operation or the data error correction operation according to the other signals of the plurality of latch control signals.Type: ApplicationFiled: September 28, 2017Publication date: October 11, 2018Applicant: SK hynix Inc.Inventor: Myung Kyun KWAK
-
Patent number: 10068632Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.Type: GrantFiled: August 22, 2017Date of Patent: September 4, 2018Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Man Keun Kang, Myung Kyun Kwak
-
Publication number: 20170352405Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: SK hynix Inc.Inventors: Geun Ho CHOI, Man Keun KANG, Myung Kyun KWAK
-
Patent number: 9779837Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.Type: GrantFiled: August 18, 2016Date of Patent: October 3, 2017Assignee: Sk hynix Inc.Inventors: Myung Kyun Kwak, Tae Yong Lee, Geun Ho Choi
-
Patent number: 9773541Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.Type: GrantFiled: July 20, 2016Date of Patent: September 26, 2017Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Man Keun Kang, Myung Kyun Kwak
-
Publication number: 20170263335Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.Type: ApplicationFiled: August 18, 2016Publication date: September 14, 2017Inventors: Myung Kyun KWAK, Tae Yong LEE, Geun Ho CHOI
-
Patent number: 9659615Abstract: A semiconductor device may include an input/output control signal generation circuit configured to generate at least one input control signal and at least one output control signal from a first control clock in response to a shifting control signal, a bank address latch circuit configured to generate a latch bank address signal by latching at least one bank address in response to the at least one input control signal and the at least one output control signal, a pipe latch circuit configured to generate an auto-precharge latch signal by latching an auto-precharge flag signal in response to the at least one input control signal and the at least one output control signal, and an auto-precharge signal generation circuit configured to generate at least one auto-precharge signal from the auto-precharge latch signal.Type: GrantFiled: June 27, 2016Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Myung Kyun Kwak, Seung Hun Lee, Tae Yong Lee
-
Publication number: 20160291082Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.Type: ApplicationFiled: July 24, 2015Publication date: October 6, 2016Inventors: Myung Kyun KWAK, Bok Rim KO