Patents by Inventor Myung S. Kim

Myung S. Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5530485
    Abstract: A channel equalizer for a high definition television that enhances the convergent speed of the channel equalizer by renewing first a filter coefficient of a near ghost image and then renewing a filter coefficient of a far ghost image, after distinguishing the filter coefficient corresponding to the near ghost image from the filter coefficient corresponding to the far ghost image.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: June 25, 1996
    Assignee: LG Electronics Co., Ltd.
    Inventors: Myung S. Kim, Hee B. Park
  • Patent number: 5475444
    Abstract: A channel equalization system of a VSB transmission system for a HDTV which can correct phase errors by using composite filters as well as by using general data even in a period having no training sequence. The channel equalizer for a HDTV includes, a composite filter part for making the input signal applied from outside produced as a I signal and a Q signal, filtering the I signal and the Q signal according to composite filter coefficients, and transmitting the filtered I and Q signals as first and second output signals.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: December 12, 1995
    Assignee: Goldstar Co., Ltd.
    Inventor: Myung S. Kim
  • Patent number: 5192992
    Abstract: A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: March 9, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung S. Kim, Jong G. Kim, Hyun S. Kim
  • Patent number: 5004573
    Abstract: A method of producing a zinc oxide varistor for high voltage which is a voltage-current non-linear type of resistor including zinc oxide as the major ingredient and bismuth oxide or manganese dioxide as additives for use with a circuit protector and gapless arrester. The method of the invention includes sintering a zinc oxide composition lacking bismuth oxide at 1200.degree.-1350.degree. C. under conditions and for a period of time effective to form a primary sintered body, heat-treating a primary sintered body coated with an amount of metal oxide paste containing mostly bismuth oxide at a temperature of 1000.degree.-1200.degree. C. for a period of time effective to diffuse the metal oxide paste to the grain boundaries of the zinc oxide grains.
    Type: Grant
    Filed: November 2, 1989
    Date of Patent: April 2, 1991
    Assignee: Korea Institute of Science and Technology
    Inventors: Myung H. Oh, Kyung J. Lee, In J. Chung, Nam Y. Lee, Myung S. Kim
  • Patent number: 4978630
    Abstract: Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor.The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current.Also, this polycrystalline silicon is used for the ion implanting mask for the extrinsic base of the NPN transistor and for the emitter, collector of the lateral PNP transistor simultaneously.Therefore, the extrinisc base of NPN transistor and the emitter, collector of the lateral PNP transistor are self-aligned by the polycrystalline silicon, and so one mask is saved by this method.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: December 18, 1990
    Assignee: Samsung Semiconductor & Telecommunication Co., Ltd.
    Inventor: Myung S. Kim
  • Patent number: 4874712
    Abstract: Present invention relates to the fabrication method of the bipolar transistor.With this method the emitter of high-concentrated n-type is contacted closely to the extrinsic base of high-concentrated p-type.This structure is obtained by making the emitter of the bipolar transistor be self- aligned by the side wall under-cut of the nitride layer using double layers of the low temperature oxide and the nitride layer.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: October 17, 1989
    Assignee: Samsung Semiconductor & Telecommunication Co., Ltd.
    Inventors: Myung S. Kim, Hyun S. Kang, Soon K. Lim, Hee K. Park
  • Patent number: 4205493
    Abstract: A portable chamfering grinding device for chamfering the end of a metal tube comprising an abrasive wheel and a portable pneumatic motor capable of rotating the wheel at greater than 10,000 r.p.m., the wheel including a diverging frustoconical portion having an inner grinding surface at an angle of about 37.5.degree. to the axis of the wheel for receiving and grinding the end of the metal tube. The inner grinding surface has eight raised, substantially trapezoidal grinding portions thereof to provide cutting edges and reduce shaking and slipping during grinding of the metal tube end.
    Type: Grant
    Filed: March 14, 1978
    Date of Patent: June 3, 1980
    Inventor: Myung S. Kim