Abstract: Provided are an apparatus and a method of managing a reconfiguration data memory. A space for a memory that stores configuration data used for reconfiguration of a target system is not provided in the target system. Instead the configuration data is stored in a separate server and, if required, the configuration data is transmitted to the target system through an Internet. Data that should be preserved after the reconfiguration among data contents stored in SoC internal and external memories of the target system is transferred to the server. The emptied space of the SoC internal and external memories is used as a configuration memory. After the reconfiguration, the preservation data is returned to its original position in the memories.

Abstract: A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

Abstract: A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

Abstract: A method of creating a ROM soft IP that can be built in a micro controller soft IP and a recording medium having a program for executing the same method are provided. The ROM soft IP capable of being built in the MPU core IP, thereby an IP designer can easily design a ROM built-in MPU soft IP. In addition, a user of the MPU core IP can create the ROM soft IP that ROM program data having a size equal to that of the program can be inserted thereinto.

Abstract: An apparatus for implementing the integrated function of virtual container-11(VC-11) and tributary unit group-2(TUG-2) is configured to transmit and receive a DS-1 network signal and a TUG-2 system signal through a synchronization process in a synchronous multiplexing structure. Data between a network and a system is converted by using only one Tx buffer and one receiving buffer in a transmitter and a receiver respectively. An input of a Tx FIFO buffer is a DS-1 signal of 1.544 Mbps, and an output thereof is a TU-11 frame of 1.728 Mbps including spaces for a path overhead and a pointer. An input of a RX FIFO buffer is the TU-11 signal of 1.728 Mbps in which the path overhead and the pointer are eliminated, and an output thereof is the DS-1 signal of 1.544 Mbps.

Abstract: Disclosed is a data and clock recovery circuit possible to restore data signals and synchronizing clocks which have been distorted during transmission over the communication line, which is comprised of the following: main oscillation loop that maintains operating frequency by using the input data and a self oscillation loop that operates using reference clock embedded within multiplex communication devices when communication lines get shorted or when power is restored after an outage; loop selecting switch which selects the main oscillation loop during normal operating mode and selects the self oscillation loop when communication line shorts or when the power is being restored; data signal monitor which connects to the loop selecting switch and determines communication line shorting by monitoring data transmission; power supply monitor which connects to the loop selecting switch and monitors the restoration of power after an outage.