Abstract: There is provided a semiconductor memory device comprising: a first word line; a second word line spaced apart from the first word line, a back gate electrode between the first word line and the second word line; a first channel pattern between the first word line and the back gate electrode; a second channel pattern between the second word line and the back gate electrode; a first gate insulating film between the first word line and the first channel pattern; a second gate insulating film between the second word line and the second channel pattern; a first bit line on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern; and a second bit line on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern.

Abstract: A vertical semiconductor device includes a plurality of channel connection patterns, a lower insulation layer, a supporting layer, a stacked structure, and a channel structure. The channel connection patterns, on which the lower insulation layer is formed, contact a substrate. The supporting layer is formed on the lower insulation layer to be spaced apart from the channel connection patterns, and includes polysilicon doped with impurities. The stacked structure is formed on the supporting layer, and includes insulation layers and gate electrodes to form a memory cell string. The channel structure passes through the stacked structure, the supporting layer and the lower insulation layer, and includes a charge storage structure and a channel which contacts the channel connection patterns. The charge storage structure and the channel face the gate electrodes and the supporting layer. The supporting layer serves as a gate of a gate induced drain leakage (GIDL) transistor.

Abstract: A vertical semiconductor device includes a plurality of channel connection patterns, a lower insulation layer, a supporting layer, a stacked structure, and a channel structure. The channel connection patterns, on which the lower insulation layer is formed, contact a substrate. The supporting layer is formed on the lower insulation layer to be spaced apart from the channel connection patterns, and includes polysilicon doped with impurities. The stacked structure is formed on the supporting layer, and includes insulation layers and gate electrodes to form a memory cell string. The channel structure passes through the stacked structure, the supporting layer and the lower insulation layer, and includes a charge storage structure and a channel which contacts the channel connection patterns. The charge storage structure and the channel face the gate electrodes and the supporting layer. The supporting layer serves as a gate of a gate induced drain leakage (GIDL) transistor.