Patents by Inventor Myung Soo Jang
Myung Soo Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240083384Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.Type: ApplicationFiled: February 3, 2023Publication date: March 14, 2024Applicants: Hyundai Motor Company, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.Inventors: Sang Soo LEE, Chan Ho JUNG, Mu Young KIM, Sang Hark LEE, Ho Suk JUNG, Deok Soo LIM, Sang Do PARK, In Sun BAEK, Sin Chan YANG, Chan Ki CHO, Myung Soo LEE, Jae Yong JANG, Jun Sik HWANG, Ho Sung KANG, Hae Dong KWAK, Hyun Tak KO
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Patent number: 10621300Abstract: A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.Type: GrantFiled: October 25, 2017Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Sig Won, Myung-Soo Jang, Hyoun-Soo Park, Da-Yeon Cho
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Patent number: 10430546Abstract: A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.Type: GrantFiled: November 3, 2017Date of Patent: October 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Sig Won, Myung-Soo Jang, Hyoun-Soo Park, Da-Yeon Cho
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Publication number: 20180173837Abstract: A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.Type: ApplicationFiled: October 25, 2017Publication date: June 21, 2018Inventors: HYO-SIG WON, MYUNG-SOO JANG, HYOUN-SOO PARK, DA-YEON CHO
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Publication number: 20180173838Abstract: A computer-implemented method. Standard cells are placed based on design data defining the integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which first through third patterns in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first through third patterns. A color violation does not occur between the first through third patterns. First, second, and third masks are generated based on the layout. A semiconductor device is manufactured by using the generated first, second, and third masks.Type: ApplicationFiled: November 3, 2017Publication date: June 21, 2018Inventors: Hyo-Sig Won, Myung-Soo Jang, Hyoun-Soo Park, Da-Yeon Cho
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Patent number: 9852256Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.Type: GrantFiled: August 4, 2014Date of Patent: December 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Myung-Soo Jang, Jae-Hwan Kim, Cheol-Jon Jang, Ji-Ho Song, Jong-Wha Chong, Kyung-In Cho
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Patent number: 9377228Abstract: The present invention provides a receiver drier for a vehicle air conditioner including: a tubular body into which a desiccant bag is inserted, and on the outer side of which a refrigerant inlet, through which a refrigerant is introduced from a condenser, and a refrigerant outlet, through which a liquid refrigerant flows out into a sub-cooling zone, are formed, the body having an opening at the lower portion thereof; a filter installed in the body; and a cap having a cap body inserted in and coupled to the opening of the body, wherein a lower part of the filter is inserted into the upper peripheral surface of the cap body, and a guide member protrudes from the top surface of the cap body toward the inner side of the filter and guides the refrigerant supplied through the refrigerant inlet to smoothly flow out through the refrigerant outlet.Type: GrantFiled: July 7, 2011Date of Patent: June 28, 2016Assignee: DOOWON CLIMATE CONTROL CO., LTDInventors: Ill Jae Lee, Myung Soo Jang
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Patent number: 9135390Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.Type: GrantFiled: June 19, 2014Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Myung-Soo Jang, Jae-Rim Lee, Jong-Wha Chong, Jae-Hwan Kim, Byung-Gyu Ahn, Cheol-Jon Jang
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Publication number: 20150137388Abstract: A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced apart from the via structure in the first low-k dielectric layer structure. The first blocking layer pattern structure surrounds a sidewall of the first blocking layer structure.Type: ApplicationFiled: November 20, 2014Publication date: May 21, 2015Inventors: Eun-Ji KIM, Sung-Dong CHO, Sin-Woo KANG, Myung-Soo JANG, Yeong-Lyeol PARK, Seung-Teak LEE
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Patent number: 9026969Abstract: A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.Type: GrantFiled: March 11, 2014Date of Patent: May 5, 2015Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation Hanyang UniversityInventors: Myung-Soo Jang, Jae-Rim Lee, Jong-Wha Chong, Min-Beom Kim, Wen Rui Li, Cheol-Jon Jang
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Publication number: 20150118793Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die perpendicular to the first die, determining a first bound region including a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die, calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.Type: ApplicationFiled: August 4, 2014Publication date: April 30, 2015Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY (IUCF-HYU)Inventors: MYUNG-SOO JANG, JAE-HWAN KIM, CHEOL-JON JANG, JI-HO SONG, JONG-WHA CHONG, KYUNG-IN CHO
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Publication number: 20140380262Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated.Type: ApplicationFiled: June 19, 2014Publication date: December 25, 2014Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: MYUNG-SOO JANG, JAE-RIM LEE, JONG-WHA CHONG, JAE-HWAN KIM, BYUNG-GYU AHN, CHEOL-JON JANG
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Publication number: 20140258949Abstract: A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.Type: ApplicationFiled: March 11, 2014Publication date: September 11, 2014Applicants: Industry-University Cooperation Foundation Hanyang University, SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-Soo JANG, Jae-Rim LEE, Jong-Wha CHONG, Min-Beom KIM, Wen Rui LI, Cheol-Jon JANG
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Publication number: 20130152625Abstract: The present invention provides a receiver drier for a vehicle air conditioner including: a tubular body into which a desiccant bag is inserted, and on the outer side of which a refrigerant inlet, through which a refrigerant is introduced from a condenser, and a refrigerant outlet, through which a liquid refrigerant flows out into a sub-cooling zone, are formed, the body having an opening at the lower portion thereof; a filter installed in the body; and a cap having a cap body inserted in and coupled to the opening of the body, wherein a lower part of the filter is inserted into the upper peripheral surface of the cap body, and a guide member protrudes from the top surface of the cap body toward the inner side of the filter and guides the refrigerant supplied through the refrigerant inlet to smoothly flow out through the refrigerant outlet.Type: ApplicationFiled: July 7, 2011Publication date: June 20, 2013Applicant: DOOWON CLIMATE CONTROL CO., LTD.Inventors: Ill Jae Lee, Myung Soo Jang