Patents by Inventor N. Deepak Swamy

N. Deepak Swamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6035350
    Abstract: A trackpad or other input/output device is detachable from a computer and adapted with a remote communication functionality using radio frequency (RF) or infrared (IR) technologies, thereby facilitating the performance of slide presentations and other graphic displays. A remote presentation capability allows a computer user to conveniently address a group from a position at a suitable location, such as a podium, that is removed from the computer system. A remote interface includes a trackpad or other input/output device and activation buttons. The input/output device is housed in a small removable enclosure which is adapted for docking into an aperture in the computer. The input/output device is rechargeable with a charger installed into the computer so that the input/output device is recharged during docking with the computer.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: March 7, 2000
    Assignee: Dell USA, L.P.
    Inventors: N. Deepak Swamy, Robert L. McMahan
  • Patent number: 5935244
    Abstract: The present invention provides a personal computer system for receiving and retaining data and capable of securing data retained within the system against unauthorized access. More particularly, the system includes a computer including a processor and a detachable input/output (I/O) device that functions as a conventional computer interface when docked to the computer and wherein the computer system enters a suspend mode when the detachable I/O device is detached from the computer whereby the system data is secured against unauthorized access. A security module controls access to at least certain levels of data retained within the system by distinguishing between the detachable I/O device docked to the computer and the detachable I/O device detached from the computer. A docking station is coupled to the processor and is detachably coupled to the detachable I/O device.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: August 10, 1999
    Assignee: Dell USA, L.P.
    Inventors: N. Deepak Swamy, Robert L. McMahan
  • Patent number: 5847951
    Abstract: An integrated circuit package comprising an integrated circuit device and a voltage converter circuit both embedded within the package. The voltage converter circuit is configured to convert a standard supply voltage to an operating voltage as required by the integrated circuit device. Also, discrete embedded capacitors may be included to capacitively couple power and ground connections of the integrated circuit device and thus reduce voltage variations during operation of the integrated circuit device. The integrated circuit may package include one or more layers. One or more discrete components or integrated circuits are mounted to one or more layers within the package. Internal conductors on one or more of the layers are configured to connect the components forming the voltage converter circuit. Internal conductors also form connections to the integrated circuit device. The integrated circuit device and voltage converter circuit may be coated with an encapsulant for added protection.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: December 8, 1998
    Assignee: Dell USA, L.P.
    Inventors: Alan E. Brown, N. Deepak Swamy
  • Patent number: 5613858
    Abstract: A circuit board structure is provided with a compact switching system for selectively connecting and disconnecting a pair of electrically conductive lead portions thereof. The switching system includes a through hole formed in the substrate portion and extending between its opposite sides. The interior side surface of the through hole is plated with an electrically conductive metal material. Portions of the plating are then removed to leave a mutually spaced plurality of plating segments within the through hole. Each plating segment is connected to an end of one of the circuit board leads. A switch structure is provided and has a contact portion which is insertable into the through hole and movable therein, into and out of engagement with a pair of the spaced plating segments, to selectively and electrically couple the circuit board leads associated with the plating segment pair.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: March 25, 1997
    Assignee: Dell U.S.A., L.P.
    Inventors: Scott H. Estes, N. Deepak Swamy
  • Patent number: 5613033
    Abstract: An interconnect system is provided in which one or more laminated modules embodying electrical devices can be stacked in a three dimensional configuration upon a printed circuit board. One or more electrical devices is surface mounted to a recessed area at the upper surface of each laminated module, and each laminated module includes male pins and female sockets. The male pins can be releasibly engaged within sockets upon a printed circuit board. Additionally, the male pins of one laminated module can be engaged within female sockets of another laminated module in building-block fashion. Conductive paths are formed entirely through the laminated module between respective sockets and pins. The conductive paths are arranged in a less dense fashion than bond locations adjacent each electrical device. The bond locations are therefore offset from conductive paths to provide fan-out and redistribution features.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: March 18, 1997
    Assignee: Dell USA, LP
    Inventors: N. Deepak Swamy, Tom J. Kocis
  • Patent number: 5587885
    Abstract: To facilitate the registered connection between a laminated multi chip module and an associated multi-tiered circuit board, spaced series of vias are formed transversely through the circuit board and module substrates between their opposite first and second sides. Gold plated BGA leads, offset from the module substrate vias, are formed on the first module substrate side on multi-layer plating structures disposed thereon and extending along the module via interior side surfaces. A spaced series of relatively shallow, circularly cross-sectioned socket areas, offset from the circuit board vias, are also formed on the first side of the circuit board. The sockets have diameters slightly larger that those of the generally ball-shaped BGA leads of the multi chip module, and are positioned on the same centerline pattern as the leads.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: December 24, 1996
    Assignee: Dell USA, L.P.
    Inventor: N. Deepak Swamy
  • Patent number: 5571608
    Abstract: An embedded core laminate including a conductive reference plane interposed between two insulation layers, and further interposed between two conductive layers. The assembly is laminated using standard temperature and pressure laminating procedures. Holes for interconnect vias are preferably drilled into the reference plane before laminating. The resulting embedded core laminate has three conductive layers with relatively uniform separation, insuring improved impedance control on each PCB (printed circuit board). Since uniform separation is maintained from one PCB to another, multiple PCBs connected together using embedded core laminates according to the present invention allows minimum cross-talk and characteristic impedance variations from one PCB to the next.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: November 5, 1996
    Assignee: Dell USA, L.P.
    Inventor: N. Deepak Swamy
  • Patent number: 5571996
    Abstract: A circuit board is provided having a plurality of vias and uniformly spaced connector stubs arranged upon one or both outer surfaces of the control board. Sets of trace conductors are formed within the control board between the vias. The trace conductors are arranged in two planes within the control board, wherein trace conductors within one plane are laterally offset from trace conductors in the other plane. Laterally offset trace conductors allow close spacing of the trace conductor planes while maximizing the spacing between trace conductors and corresponding reference conductors also placed within the control board. Additionally, the trace conductors are serpentine-shaped when viewed from a perspective perpendicular to the planar surface of the control board.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: November 5, 1996
    Assignee: Dell USA, L.P.
    Inventors: N. Deepak Swamy, Victor K. Pecone, Darrell Slupek
  • Patent number: 5541368
    Abstract: To facilitate the reworking of a multi-tiered circuit board and a laminated multi chip module, a chip module apparatus having a substrate portion is provided. The chip module has first and second opposite sides with vias extending therethrough. Deposited on both sides of the module by conventional processes is a layer of copper. A first mask is applied to the copper layer to expose a copper, electrical circuit pattern. A second mask having holes therein that are offset from the vias is placed over the first mask by conventional processes. Formed on at least one of the chip module's side in the second mask's holes are a spaced series of an solder BGAs, which have melting point temperatures substantially greater than the phase transition temperature of the chip module's substrate portion. The BGA's are formed on the chip module by an electrochemical plating process.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: July 30, 1996
    Assignee: Dell USA, L.P.
    Inventor: N. Deepak Swamy
  • Patent number: 5541367
    Abstract: A printed circuit board is provided having one or more lands formed upon the outer surface of the printed circuit board. Each land is adapted to receive a surface mount component and, specifically, leads extending from the surface mount component. Each land is fabricated having an inwardly facing exposed surface which, when the lead is placed upon the land, directs or channels the lead toward the center of the land to enhance interconnect accuracy of the lead to the land. Moreover, various configurations of solder are placed upon the land, wherein the solder can be deposited at select regions on the land or at a controlled thickness. Careful placement of solder helps ensure the lead, once placed, will not migrate or misalign from the land during subsequent reflow. Careful placement of solder helps minimize surface tension imbalance of the molten solder by assuring surface migration in a controlled direction to the middle of the land.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: July 30, 1996
    Assignee: Dell USA, L.P.
    Inventor: N. Deepak Swamy
  • Patent number: 5420378
    Abstract: To facilitate a grounding connection between a circuit board and a chassis upon which it is to be mounted, a spaced series of unlined mounting holes are formed through the substrate portion of the circuit board between its top and bottom sides, and spaced series of grounding vias are formed through the substrate and positioned in a circular arrays around each of the mounting holes. Annular layers of a metallic plating material are formed on the opposite sides of the circuit board substrate, around the top and bottom ends of the unlined mounting holes, with the plating material being extended along the interior side surfaces of the vias between associated top and bottom annular plating material layers.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: May 30, 1995
    Assignee: Dell USA, L.P.
    Inventors: H. Scott Estes, Michael Ohlinger, N. Deepak Swamy