Abstract: A memory cell for a three-dimensional intergrated circuit memory is disclosed. The cell includes a very highly doped semiconductor regions with a doping level of 1020 atoms cm−3 or higher. An antifuse region is disposed between the heavily doped region and a more lightly doped region.

Abstract: A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer having a precise thickness and uniformity. The high density plasma oxidation process can be used to fabricate gate oxide layers, passivation layers and antifuse layers in semiconductor devices such as semiconductor memory devices and multi-level memory arrays.

Abstract: The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material.

Abstract: A digital memory array includes memory cells having respective anti-fuse layers. Write signals that vary in at least one of current, voltage, and pulse length are applied to selected ones of the memory cells to disrupt the respective anti-fuse layers to differing extents, thereby programming the selected memory cells with resistances that vary in accordance with the degree of anti-fuse layer disruption. The state of a selected memory cell is read by applying a voltage across the cell and comparing the resulting read signal with two or more thresholds, thereby reading more than one bit of digital data from each memory cell.

Abstract: The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features.

Abstract: A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Abstract: The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material.

Abstract: A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.

Abstract: A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Abstract: The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure.

Abstract: The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features. The gap between the features is filled with the dielectric material which is softer than the masking layer with respect to a planarization step. The dielectric material is then planarized with the masking layer acting as a polish stop.

Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract: An arithmetic unit for adding a plurality of values to define a result, said arithmetic unit comprising means for receiving said plurality of values; means for adding said plurality of values to define a result, said result being within a first range; means for determining if said result fall within a second range, said second range being smaller than the first range, said means being arranged to consider only some of the bits of said result; and means for modifying said result in so that the result output by said arithmetic unit falls within the second range.

Abstract: A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.

Abstract: An electron-emitting device is fabricated by a process in which particles (46) are distributed over an initial structure. The particles are utilized in defining primary openings (52, 64, or 78) that extend through a primary layer (50A, 62A, or 72) provided over a gate layer (48A, 60A, or 60B) formed over an insulating layer (44) and in defining corresponding gate openings (54, 66, or 80) that extend through the gate layer. The insulating layer is etched through the primary and gate openings to form corresponding dielectric openings (56 or 68) through the insulating layer down to a lower non-insulating region (42). Electron-emissive elements (58A or 70A) are formed over the lower non-insulating region so that each electron-emissive element is at least partially situated in one dielectric opening.

Abstract: Excess emitter material (52B) is removed in multiple steps during the fabrication of an electron-emitting device. A structure is initially provided in which a dielectric layer (44) overlies a non-insulating region (42), control electrodes (80 or 46/80) overlie the dielectric layer, openings (48/50) extend through the control electrodes and dielectric layer, electron-emissive elements (52A) formed with emitter material are situated in the openings, and an excess layer (52B) of the emitter material overlies the control electrodes and the dielectric layer. Portions of the excess emitter material overlying the dielectric layer in the spaces between the control electrodes are initially removed, preferably with etchant that directly attacks the emitter material. Portions (52C) of the excess emitter material overlying the control electrodes above the electron-emissive elements are subsequently removed to expose the electron-emissive elements.

Abstract: A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (102A, 110A, 124A, 140, or 150B). Dielectric openings (80, 114, 128, 144, or 154) are formed through the insulating layer. The dielectric openings can be created before or after creating the spacers.

Abstract: An electron-emitting device employs a multi-layer resistor (46). A lower layer (48) of the resistor overlies an emitter electrode (42). A set of electron-emissive elements (54) overlie an upper layer (50) of the resistor. Each resistive layer extends continuously from a location below each electron-emissive element to a location below each other electron-emissive element. The two resistive layers are of different chemical composition. The upper resistive layer is typically formed with cermet. The lower resistive layer is typically formed with a silicon-carbon compound.

Abstract: An electron-emitting device contains an electron focusing system (37 or 37A) formed with a base focusing structure (38 or 38A) and a focus coating (39 or 39A) that penetrates partway into a focus opening (40) extending through the base focusing structure above an electron-emissive element (24). The focus coating is normally of lower resistivity than the base focusing structure and thereby provides most of the focus control over electrons emitted by the electron-emissive element. The focus coating is typically formed by an angled deposition technique.

Abstract: In a partially finished electron-emitting device having electron-emissive elements (56A) formed at least partially with electrically non-insulating emitter material, electron-emissive element contamination that could result from passage of contaminant material through an excess layer (56B) of the emitter material is inhibited by forming a protective layer (58 or 70) over the excess emitter-material layer before performing additional processing operations on the electron-emitting device. Subsequent to these processing operations, material of the excess and protective layers overlying the electron-emissive elements is removed to expose the electron-emissive elements.