Patents by Inventor N. Srinivas

N. Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7539869
    Abstract: In a networked computer environment, a client is unencumbered from signature generating components, yet conversant to transmit signature-based documents in a signature-based metalanguage such as XML. The nonsigning client/user invokes a signature from a signature server to send a payload of data in a signed message format to a recipient also conversant in the metalanguage, according to the metalanguage format. The nonsigning client receives a signature block including a signature value from the server. The client identifies a payload for transmission according to the metalanguage. Employing the metalanguage interpreter in client, the client stores the payload data in the signature block without disrupting the signature and the data it covers in the signature block. The nonsigning client the sends the resulting signature message including the payload data and the signature value, in the metalanguage format, to the recipient destination conversant in the metalanguage.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 26, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Sean J. Mullan, Raghavan N. Srinivas
  • Patent number: 7512925
    Abstract: A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Parag Birmiwal, Tilman Gloekler, Mack W. Riley, Devi Shanmugam, Polisetty V. N. Srinivas
  • Publication number: 20080034261
    Abstract: A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
    Type: Application
    Filed: July 14, 2006
    Publication date: February 7, 2008
    Inventors: Parag Birmiwal, Tilman Gloekler, Mack W. Riley, Devi Shanmugam, Polisetty V.N. Srinivas
  • Publication number: 20060288341
    Abstract: Runtime patch validation is provided that instruments an in-use function to determine whether the function needs a patch and/or how the patch will impact the function. Patch validation code is instrumented into a target binary when the target binary is running. Patch validation data is gathered from the instrumented target binary and provided for viewing and analysis.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Applicant: Microsoft Corporation
    Inventors: Frederick Wurden, David MacDonald, Eric Bahna, N. Srinivas, Patrick Chiu, Paul Donlan
  • Publication number: 20040263179
    Abstract: A method and apparatus for on-line detection of partial discharge events in an a.c. power system, in which high frequency electromagnetic pulses generated by partial discharge events are detected and analyzed in the frequency domain and the time domain to determine the type and location of the partial discharge event. The phase relationship between the partial discharge events and the on-line power signal is also examined to help indicate severity of the insulation anomaly giving rise to the partial discharge events.
    Type: Application
    Filed: July 20, 2004
    Publication date: December 30, 2004
    Inventors: Nezar Ahmed, N. Srinivas
  • Patent number: 4353794
    Abstract: A process for the solvent extraction of aromatic hydrocarbons from a mixture thereof with non-aromatic hydrocarbons, and for the recovery of a non-aromatic fraction substantially free of aromatic hydrocarbons, is disclosed. Said mixture is treated with an aromatic-selective solvent in a first extraction zone to provide an aromatic-rich solvent stream and a non-aromatic raffinate stream. The rich solvent stream is treated in a first solvent recovery zone to provide a high purity aromatic stream and a lean solvent stream. One portion of the lean solvent stream is recycled to the first extraction zone, and residual aromatic hydrocarbons are stripped from the remaining portion. This aromatics-free solvent is then utilized to extract residual aromatics from a fraction of the non-aromatic raffinate to provide a high purity paraffin stream.
    Type: Grant
    Filed: November 26, 1980
    Date of Patent: October 12, 1982
    Assignee: UOP Inc.
    Inventors: George R. Winter, III, William H. Maier, K. N. Srinivas Prabhu