Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.