Abstract: A zero-watermarking method and device for BIM data, and a medium are provided, which relate to the field of watermarking information security technologies. Aiming at existing zero-watermarking method for the BIM data cannot resist primitive attacks, vertical stability of a model is used to construct a mapping relationship between primitive clusters and watermarking bits, calculate norms of primitives in each primitive cluster of the primitive clusters, take positivity and negativity of norm skewness measurement of the primitives as eigenvalues to construct a binary sequence, and performs an XOR process on the binary sequence and an original watermarking sequence to construct the zero-watermarking for the BIM data. Experimental results indicate that the zero-watermarking method has uniqueness, robustness and security.

Abstract: A dual watermarking method for trajectory data based on robust watermarking and fragile watermarking uses an encryption algorithm to construct robust watermark information, and then a farthest pair of feature points in a minimum convex hull of is set as constant points. Further quantization index modulation technology is used to embed robust watermark information into angles constructed from feature points and constant points. Finally, the angles and distance ratios constructed by trajectory points and constant points are used to group trajectory points. Within each group, spatiotemporal attributes of the trajectory points are taken as fragile watermark bits to be embedded in the distance ratios constructed by the trajectory points. A process of watermark detection is consistent with the embedding of watermark information. Watermarks embedded in the trajectory data based on the dual watermarking method have high robustness against translation, rotation, and scaling attacks.

Abstract: A watermarking method for a high-definition map based on invisible characters includes: firstly, establishing mapping relations between invisible characters and bit characters, a space character, and decimal digits; and combining watermark characters with corresponding positions thereof, adding Hamming code into a watermark character sequence, and converting the watermark character sequence into invisible characters to construct a composite watermark character sequence. Before watermark detection, a sequence of elements in map data is scrambled according to logistic chaotic mapping, and then the composite watermark character sequence is embedded according to the scrambled sequence. During watermark detection, the data are preprocessed, a sequence during watermark embedding is obtained, and then watermark information is extracted, errors are corrected, and an error correcting code is removed after correction to obtain final watermark information.

Abstract: A generation method of zero watermarking for trajectory data, a detection method of zero watermarking for trajectory data, a generation device of zero watermarking for trajectory data, a detection device of zero watermarking for trajectory data, and a storage medium are provided. The generation method divides a trajectory based on a coordinate system constructed by trajectory feature points of trajectory data into blocks, and then the moment invariants of trajectory in each block are used to construct a watermark sequence, which can achieve copyright protection without modifying the trajectory data. In addition, since the generation method uses moment invariants which can represent overall features of the trajectory to construct the watermark sequence, the generation method has strong stability in the face of common attacks and can resist almost all common types of attacks.

Abstract: A fast-turn-on floating island device and a method for manufacturing thereof in the field of semiconductor technology. The device comprises a surface layer, a bottom layer and a drift layer which is located between the surface layer and the bottom layer, wherein, the drift layer comprises a plurality of epitaxial layers and a plurality of floating island layers, one of the floating island layers formed between adjacent two of the epitaxial layers, or one of the epitaxial layers between adjacent two of the floating island layers, a first doped region and a second doped region form in at least one of the floating island layers.

Abstract: A trench-gate power MOSFET with optimized layout, comprising: a substrate; a first semiconductor region formed on the substrate, having a first doping type; mutually separated trench isolation gate structure, formed on the first semiconductor region, the trench isolation gate structure includes an gate oxide layer and a gate electrode; a second semiconductor region and a third semiconductor region formed between any two adjacent structures of mutually separated trench isolation gate structures; and a first shielding region, formed under each of the third semiconductor regions, connecting simultaneously with multiple mutually separated trench isolation structures.

Abstract: The present disclosure provides a silicon carbide trench gate metal oxide semiconductor field effect transistor (MOSFET) and a method for manufacturing thereof. The silicon carbide trench gate MOSFET includes: a substrate having a first doping type, an epitaxial layer formed on the substrate and having the first doping type, an epitaxial well region formed above the epitaxial layer and having a second doping type, a first source contact region formed in the epitaxial well region and having the first doping type, a second source contact region formed in the epitaxial well region and having the second doping type, a trench gate, a source electrode and a drain electrode, wherein the trench gate includes a gate dielectric and a gate electrode, the silicon carbide trench gate MOSFET further includes a injection-type current diffusion region, which is wrapped around the bottom of the trench gate and has the first doping type.

Abstract: A trench-gate power MOSFET with optimized layout, comprising: a substrate; a first semiconductor region formed on the substrate, having a first doping type; mutually separated trench isolation gate structure, formed on the first semiconductor region, the trench isolation gate structure includes an gate oxide layer and a gate electrode; a second semiconductor region and a third semiconductor region formed between any two adjacent structures of mutually separated trench isolation gate structures; and a first shielding region, formed under each of the third semiconductor regions, connecting simultaneously with multiple mutually separated trench isolation structures.

Abstract: A trench gate silicon carbide MOSFET with high reliability, including: An N+ type substrate, an N? type drift region, a first P type region, a P+ type contact region, an N+ type contact region, an N type equivalent resistance region between the first P type region and the N+ type contact region, a gate dielectric layer, a trench gate, an isolation dielectric layer, a source electrode and a drain electrode.

Abstract: A trench-gate MOSFET with electric field shielding region, has a substrate; a source electrode; a drain electrode; a semiconductor region with a first doping type formed on the substrate; a trench-gate, a plurality of electric field shielding regions with a second doping type formed under a surface of the semiconductor region, wherein the electric field shielding region intersects the trench-gate at an angle; a source electrode region formed on both sides of the trench-gate is divided into a plurality of source electrode sub-regions by the plurality of electric field shielding regions.

Abstract: A silicon carbide power MOSFET with enhanced body diode applying a repetitive polygonal or circular layout design on a first surface, having: a substrate; an N-type SiC region with a first doping concentration formed on the substrate; a JFET region or a trench insulating gate region formed inside the N-type SiC region; a metal layer formed on the N-type SiC region; a P-type SiC region with a second doping concentration or a Schottky region, wherein the P-type SiC region is formed on one side of the JFET region or one side of the trench insulating gate region, the P-type SiC region and the metal layer are contacted directly forming an ohmic contact, the Schottky region and the metal layer are contacted directly forming a Schottky contact; and a conventional source region on another side of the JFET region.

Abstract: A method for manufacturing a Silicon Carbide (SiC) Schottky diode may include steps of providing a substrate; forming a first epitaxial layer with a first conductivity type on top of the substrate; forming a second epitaxial layer with a second conductivity type on top of the first epitaxial layer; forming a third epitaxial layer with the second conductivity type on top of the second epitaxial layer; patterning and etching the second and third epitaxial layers to form a plurality of trenches; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the second epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal.

Abstract: In one aspect, a method for manufacturing an analog integrated circuit with improved transistor lifetime includes steps of: providing a P-type substrate; forming N+ source/drain regions; forming a P+ isolation island to separate a high voltage I/O transistor and low voltage core transistor; patterning a SiON dielectric layer on one side of the P+ isolation island for the high voltage I/O transistor; patterning a SiO2 dielectric layer on the other side of the P+ isolation island for the low voltage core transistor; forming a gate structure for the low voltage core transistor and high voltage I/O transistor; forming a gate polysilicon layer on a top portion of each of the SiO2 and SiON dielectric layers; forming a SiON passivation layer with open holes; and forming a source electrode, a gate electrode and a drain electrode for each of the low voltage core transistor and high voltage I/O transistor.

Abstract: A Schottky diode may include a substrate; an epitaxial layer deposited on top of the substrate; one or more trenches formed on top of the epitaxial layer; an implantation region at a bottom portion of each trench; an ohmic contact metal on the other side of the substrate; a first Schottky contact metal deposited onto the implantation region in each trench to form a first Schottky junction between the first Schottky contact metal and the epitaxial layer at a lower trench sidewall; a second Schottky contact metal filling each trench and extending a predetermined length to each corner of mesas on the epitaxial layer to form a second Schottky junction between the second Schottky contact metal and the epitaxial layer at an upper trench sidewall; and a third Schottky contact metal covering the second Schottky contact metal and the epitaxial layer to form a third Schottky junction.

Abstract: In one aspect, a method for manufacturing a silicon carbide (SiC) multi-Schottky-layer trench junction barrier Schottky diode may include steps of providing a substrate; forming an epitaxial layer on top of the substrate; forming one or more trenches on the epitaxial layer; generating a first implantation region at a bottom portion of each trench; providing an ohmic contact metal on an opposite of the substrate; generating a second implantation region at each corner near a top portion of each trench; and forming a Schottky contact metal to fill in each trench and on top of the epitaxial layer.

Abstract: In one aspect, a semiconductor device comprising an electronic conductive Silicon Carbide (SiC) substrate; a semi-insulating or insulating SiC epitaxial layer formed on the electronic conductive SiC substrate; and a Gallium Nitride (GaN) device formed on the semi-insulating or insulating SiC epitaxial layer. In one embodiment, the semi-insulating or insulating SiC epitaxial layer is grown directly on the SiC substrate through chemical vapor deposition (CVD). In another embodiment, the GaN device is a high electron mobility transistor (HEMT).

Abstract: A manufacturing method for a LDMOS semiconductor device may include steps of forming a P-type layer on a P-type substrate; forming a P-type body region and an N-type well under the P-type layer; forming a field oxide on the P-type layer; forming a gate oxide on the P-type body region and field oxide; forming a gate polysilicon on top of the gate oxide; depositing a gate metal silicide on top of the gate polysilicon; depositing a thin film on top of the field oxide, P-type body region and gate silicide; forming a dielectric layer on top of the thin film; forming a first trench in the dielectric layer; forming a second trench underneath the first trench; depositing a metal layer on top of the dielectric layer and filling into the first and second trenches; and removing the metal on top of the dielectric layer.

Abstract: A method for manufacturing a SiC mixed trench Schottky diode may include steps of providing a substrate and an epitaxial layer on top of the substrate; forming a plurality of trenches on a surface of the epitaxial layer; conducting ion implantation at a bottom portion of each trench; conducting ion implantation at sidewalls of each trench; forming an ohmic contact metal at a bottom portion of the Schottky diode; forming a Schottky contact metal on top of the epitaxial layer and in the trenches. In one embodiment, the substrate is an N+ type SiC and the epitaxial layer is an N? type SiC. In another embodiment, the step of forming a plurality of trenches on a surface of the epitaxial layer may include the step of etching the surface of the epitaxial layer by either dry etching or wet etching.

Abstract: A method for manufacturing a SiC mixed trench Schottky diode may include steps of providing a substrate and an epitaxial layer on top of the substrate; forming a plurality of trenches on a surface of the epitaxial layer; conducting ion implantation at a bottom portion of each trench; conducting ion implantation at sidewalls of each trench; forming an ohmic contact metal at a bottom portion of the Schottky diode; forming a Schottky contact metal on top of the epitaxial layer and in the trenches. In one embodiment, the substrate is an N+ type SiC and the epitaxial layer is an N? type SiC. In another embodiment, the step of forming a plurality of trenches on a surface of the epitaxial layer may include the step of etching the surface of the epitaxial layer by either dry etching or wet etching.

Abstract: A method for manufacturing a Silicon Carbide (SiC) Schottky diode may include steps of providing a substrate; forming a first epitaxial layer with a first conductivity type on top of the substrate; forming a second epitaxial layer with a second conductivity type on top of the first epitaxial layer; forming a third epitaxial layer with the second conductivity type on top of the second epitaxial layer; patterning and etching the second and third epitaxial layers to form a plurality of trenches; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the second epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal.