Patents by Inventor Nabil Imam
Nabil Imam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979148Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: May 7, 2024Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11909391Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: February 20, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11901891Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: February 13, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11863184Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11855627Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 13, 2022Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11855626Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11817859Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1 V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: November 14, 2023Assignee: KEPLER COMPUTING INC.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11811402Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: November 7, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Publication number: 20230251828Abstract: Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit.Type: ApplicationFiled: February 7, 2022Publication date: August 10, 2023Applicant: Kepler Computing Inc.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11716086Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716084Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716085Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716083Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Publication number: 20230223936Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: ApplicationFiled: January 14, 2022Publication date: July 13, 2023Applicant: Kepler Computing Inc.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11658664Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: May 23, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11652487Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: May 16, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11652482Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: May 16, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Publication number: 20220198245Abstract: A computer-implemented method of training a neural network to recognize sensory patterns includes obtaining input data, preprocessing the input data in one or more preprocessors of the neural network, and applying the preprocessed input data to a core portion of the neural network. The core portion of the neural network includes a plurality of principal neurons and a plurality of interneurons, and is configured to implement a feedback loop from the interneurons to the principal neurons that supports persistent unsupervised differentiation of multiple learned sensory patterns over time. The method further includes obtaining an output from the core portion, and performing at least one automated action based at least in part on the output obtained from the core portion. The neural network may be adaptively expanded to facilitate the persistent unsupervised differentiation of multiple learned sensory patterns over time by incorporating additional interneurons into at least the core portion.Type: ApplicationFiled: April 10, 2020Publication date: June 23, 2022Inventors: Thomas A. Cleland, Nabil Imam, Ayon Borthakur
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Patent number: 10885425Abstract: A spiking neural network (SNN) includes artificial neurons interconnected by artificial synapses to model a particular network. A first neuron emits spikes to neighboring neurons to cause a wave of spikes to propagate through the SNN. Weights of a portion of the synapses are increased responsive to the wave of spikes based on a spike timing dependent plasticity (STDP) rule. A second neuron emits spike to cause a chain of spikes to propagate to the first neuron on a path based on the increase in the synaptic weights. The path is determined to represent a shortest path in the particular network from a first network node represented by the second neuron to a second network node represented by the first neuron.Type: GrantFiled: December 20, 2016Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Nabil Imam, Narayan Srinivasa
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Patent number: 10846590Abstract: A spike timing dependent plasticity (STDP) rule is applied in a spiking neural network (SNN) that includes artificial synapses bi-directionally connecting artificial neurons in the SNN to model locations within a physical environment. A first neuron is activated to cause a spike wave to propagate from the first neuron to other neurons in the SNN. Propagation of the spike wave causes synaptic weights of a subset of the synapses to be increased based on the STDP rule. A second neuron is activated after propagation of the spike wave to cause a spike chain to propagate along a path from the second neuron to the first neuron, based on the changes to the synaptic weights. A physical path is determined from the second to the first neuron based on the spike chain, and a signal may be sent to a controller of an autonomous device to cause the autonomous to navigate the physical path.Type: GrantFiled: December 20, 2016Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Nabil Imam, Narayan Srinivasa