Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.

Abstract: This transmission system comprises a station of a first type and a plurality of stations of a second type which include a transmitting part having a transmit timing controller for transmitting data at a transmit timing and a receiving part having synchronizing circuits for synchronization with data transmitted from the station of the first type. When the stations of the second type are moving, their transmit timing is modified to facilitate the synchronization of the reception of the station by solely being based on the receive timing at these stations of the second type.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Abstract: A wireless terminal includes a line interface which is connectable to a modem of an external apparatus. A controller of the wireless terminal is connected to the line interface. In response to connection of the wireless terminal to the modem, the controller switches the wireless terminal from a telephony mode into a transparent transmission mode for transmitting signals received from the modem to a communication network via an air interface.

Abstract: This data transmission system satisfies a specification of the type 3G TS 25.211 and, while using spread spectrum codes, is formed by at least a transmission part (10) for transmitting the data by using spread spectrum codes and at least a receiving part (20) for receiving said data. In this system first data are transmitted over the channel CPICH for a period of time that is relatively long, whereas second data are transmitted over the channel SCH for period of time that a relatively short. It is suggested that the second data be transmitted during the interruptions of the transmission of the first data, or also with an attenuation of this transmission.

Abstract: The input data to a CDMA transmitter is used to introduce a slight frequency offset to the clock that is used to generate the CDMA code. At the receiver, the frequency-offset CDMA signal proportionately affects the magnitude of output signals from one or more CDMA correlators. A composite signal that is based on the magnitudes of the output signals is compared to a set of predefined threshold levels to provide the demodulated output data.

Abstract: The input data to a CDMA transmitter is used to introduce a slight frequency offset to the clock that is used to generate the CDMA code. At the receiver, the frequency-offset CDMA signal proportionately affects the magnitude of output signals from one or more CDMA correlators. A composite signal that is based on the magnitudes of the output signals is compared to a set of predefined threshold levels to provide the demodulated output data.

Abstract: This transmission system comprises a station of a first type (1) and a plurality of stations of a second type (2, 3, 4, . . . ) which include a transmitting part (T) having a transmit timing controller for transmitting data at a transmit timing and a receiving part (R) having synchronizing circuits for synchronization with data transmitted from the station of the first type. When the stations of the second type are moving, their transmit timing is modified to facilitate the synchronization of the reception of the station (1) by solely being based on the receive timing at these stations of the second type.