Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.

Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.

Abstract: The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.

Abstract: A new method to monitor sheet resistance of a metal silicide layer in the manufacture of an integrated circuit device is achieved. The method comprises providing a metal silicide layer overlying an exposed silicon layer on a substrate. A thermal wave intensity signal is generated for the metal silicide layer by an optical measurement system. The optical measurement system comprises a first laser beam that is intensity modulated and a second laser beam. The first and second laser beams comprise different wavelengths. A dichroic mirror is used to combine the first and second laser beams and to project the first and second laser beams onto the metal silicide layer. A detector is used to gather the second laser beam reflected from the metal silicide layer and to generate a thermal wave intensity signal based on the reflected second laser beam. Sheet resistance of the metal silicide layer is calculated by a linear equation based on the thermal wave intensity signal.

Abstract: The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. The trench isolation structure, in accordance with the principles of the present invention, may include a substrate having a trench located therein, and an isolation material located within the trench, wherein the isolation material has no undercut at corners where the isolation material meets the substrate.

Abstract: The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.

Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.

Abstract: A new method is provided for the creation of an adhesion/barrier layer over which a tungsten interconnect is created. The invention reduces metal extrusion and effects of pin-holes by dividing the process of barrier material of TiN deposition into phases, whereby after about half the thickness of the required layer of TiN has been deposited, an intermediate and very thin layer of Ti is deposited. After the thin layer of Ti has been deposited, the deposition of the barrier layer of TiN is continued to the point where the required thickness for the layer of TiN has been reached.

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.

Abstract: A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like.

Abstract: The present invention provides a capacitor comprising a conductive plug comprising a top surface and exposed sidewalls, wherein the sidewalls comprise a layer selected from the group consisting of titanium and titanium nitride, and an electrode material layer over the conductive plug sidewalls, wherein the layer of electrode material is not titanium nor titanium nitride.

Abstract: A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.

Abstract: A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: Method for forming metal lines during the fabrication of an integrated circuit including the step of stripping a photoresist layer to expose a patterned antireflective coating layer prior to performing a metal etch. A semiconductor substrate is prepared with a metal layer for the formation of metal lines. The photoresist is exposed and developed after being deposited on an antireflective coating that has been deposited on a composite metal stack. The method includes etching the antireflective coating, stripping the photoresist, etching a composite metal stack to form the metal lines, removing the antireflective coating and cleaning the metal stack. A device at this stage of manufacture is also disclosed.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.

Abstract: A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.