Patents by Inventor Nace M. Rossi

Nace M. Rossi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8372723
    Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: February 12, 2013
    Assignee: Agere Systems LLC
    Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 8367497
    Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 5, 2013
    Assignee: Agere Systems LLC
    Inventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Patent number: 8106480
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: January 31, 2012
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Publication number: 20110312146
    Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.
    Type: Application
    Filed: August 31, 2011
    Publication date: December 22, 2011
    Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 8049282
    Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: November 1, 2011
    Assignee: Agere Systems Inc.
    Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 7923340
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Patent number: 7898038
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: March 1, 2011
    Assignee: Agere Systems, Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Publication number: 20100264478
    Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 21, 2010
    Applicant: Agere Systems Inc.
    Inventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Publication number: 20100102418
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.
    Type: Application
    Filed: January 5, 2010
    Publication date: April 29, 2010
    Applicant: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Publication number: 20100065920
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
    Type: Application
    Filed: February 14, 2007
    Publication date: March 18, 2010
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Patent number: 7666750
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: February 23, 2010
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Publication number: 20090236668
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Application
    Filed: June 2, 2009
    Publication date: September 24, 2009
    Applicant: LSI Corporation
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Patent number: 7557010
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: July 7, 2009
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Publication number: 20090050977
    Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
    Type: Application
    Filed: October 23, 2008
    Publication date: February 26, 2009
    Applicant: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Patent number: 7479438
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: January 20, 2009
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 7456061
    Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: November 25, 2008
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Publication number: 20080237642
    Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Publication number: 20080191246
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 14, 2008
    Applicant: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Publication number: 20080076228
    Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Applicant: Agere Systems Inc.
    Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Publication number: 20080064177
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.
    Type: Application
    Filed: September 13, 2006
    Publication date: March 13, 2008
    Applicant: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi