Patents by Inventor Nace M. Rossi
Nace M. Rossi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8372723Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.Type: GrantFiled: August 31, 2011Date of Patent: February 12, 2013Assignee: Agere Systems LLCInventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Patent number: 8367497Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.Type: GrantFiled: October 31, 2007Date of Patent: February 5, 2013Assignee: Agere Systems LLCInventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Patent number: 8106480Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.Type: GrantFiled: January 5, 2010Date of Patent: January 31, 2012Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Publication number: 20110312146Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.Type: ApplicationFiled: August 31, 2011Publication date: December 22, 2011Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Patent number: 8049282Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.Type: GrantFiled: September 21, 2006Date of Patent: November 1, 2011Assignee: Agere Systems Inc.Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Patent number: 7923340Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.Type: GrantFiled: February 14, 2007Date of Patent: April 12, 2011Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Patent number: 7898038Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.Type: GrantFiled: June 2, 2009Date of Patent: March 1, 2011Assignee: Agere Systems, Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Publication number: 20100264478Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.Type: ApplicationFiled: October 31, 2007Publication date: October 21, 2010Applicant: Agere Systems Inc.Inventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Publication number: 20100102418Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.Type: ApplicationFiled: January 5, 2010Publication date: April 29, 2010Applicant: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Publication number: 20100065920Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.Type: ApplicationFiled: February 14, 2007Publication date: March 18, 2010Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Patent number: 7666750Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.Type: GrantFiled: September 13, 2006Date of Patent: February 23, 2010Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Publication number: 20090236668Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.Type: ApplicationFiled: June 2, 2009Publication date: September 24, 2009Applicant: LSI CorporationInventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Patent number: 7557010Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.Type: GrantFiled: February 12, 2007Date of Patent: July 7, 2009Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Publication number: 20090050977Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.Type: ApplicationFiled: October 23, 2008Publication date: February 26, 2009Applicant: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Patent number: 7479438Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.Type: GrantFiled: August 31, 2006Date of Patent: January 20, 2009Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Patent number: 7456061Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.Type: GrantFiled: March 30, 2007Date of Patent: November 25, 2008Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Publication number: 20080237642Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Publication number: 20080191246Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Applicant: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Publication number: 20080076228Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.Type: ApplicationFiled: September 21, 2006Publication date: March 27, 2008Applicant: Agere Systems Inc.Inventors: Mark Dyson, Daniel C. Kerr, Nace M. Rossi
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Publication number: 20080064177Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.Type: ApplicationFiled: September 13, 2006Publication date: March 13, 2008Applicant: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi