Abstract: The present invention relates to the digital circuits for evaluating neural engineering framework style neural networks. The digital circuits for evaluating neural engineering framework style neural networks comprised of at least one on-chip memory, a plurality of non-linear components, an external system, a first spatially parallel matrix multiplication, a second spatially parallel matrix multiplication, an error signal, plurality of set of factorized network weight, and an input signal. The plurality of sets of factorized network weights further comprise a first set factorized network weights and a second set of factorized network weights. The first spatially parallel matrix multiplication combines the input signal with the first set of factorized network weights called the encoder weight matrix to produce an encoded value. The non-linear components are hardware simulated neurons which accept said encoded value to produce a distributed neural activity.

Abstract: The present invention relates to the digital circuits for evaluating neural engineering framework style neural networks. The digital circuits for evaluating neural engineering framework style neural networks comprised of at least one on-chip memory, a plurality of non-linear components, an external system, a first spatially parallel matrix multiplication, a second spatially parallel matrix multiplication, an error signal, plurality of set of factorized network weight, and an input signal. The plurality of sets of factorized network weights further comprise a first set factorized network weights and a second set of factorized network weights. The first spatially parallel matrix multiplication combines the input signal with the first set of factorized network weights called the encoder weight matrix to produce an encoded value. The non-linear components are hardware simulated neurons which accept said encoded value to produce a distributed neural activity.