Patents by Inventor Nachiket Raravikar

Nachiket Raravikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9795038
    Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Nachiket Raravikar
  • Patent number: 9669425
    Abstract: A thermally and electrically conductive structure comprises a carbon nanotube (110) having an outer surface (111) and a carbon coating (120) covering at least a portion of the outer surface of the carbon nanotube. The carbon coating may be applied to the carbon nanotube by providing a nitrile-containing polymer, coating the carbon nanotube with the nitrile-containing polymer, and pyrolyzing the nitrile-containing polymer in order to form the carbon coating on the carbon nanotube. The carbon nanotube may further be coated with a low contact resistance layer (130) exterior to the carbon coating and a metal layer (140) exterior to the low contact resistance layer.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Linda Shekhawat, Nachiket Raravikar
  • Publication number: 20160095220
    Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Omkar Karhade, Nitin Deshpande, Nachiket Raravikar
  • Publication number: 20150367378
    Abstract: A thermally and electrically conductive structure comprises a carbon nanotube (110) having an outer surface (111) and a carbon coating (120) covering at least a portion of the outer surface of the carbon nanotube. The carbon coating may be applied to the carbon nanotube by providing a nitrile-containing polymer, coating the carbon nanotube with the nitrile-containing polymer, and pyrolyzing the nitrile-containing polymer in order to form the carbon coating on the carbon nanotube. The carbon nanotube may further be coated with a low contact resistance layer (130) exterior to the carbon coating and a metal layer (140) exterior to the low contact resistance layer.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Applicant: INTEL CORPORATION
    Inventors: Linda Shekhawat, Nachiket Raravikar
  • Patent number: 9214420
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh
  • Patent number: 9159464
    Abstract: A thermally and electrically conductive structure comprises a carbon nanotube (110) having an outer surface (111) and a carbon coating (120) covering at least a portion of the outer surface of the carbon nanotube. The carbon coating may be applied to the carbon nanotube by providing a nitrile-containing polymer, coating the carbon nanotube with the nitrile-containing polymer, and pyrolyzing the nitrile-containing polymer in order to form the carbon coating on the carbon nanotube. The carbon nanotube may further be coated with a low contact resistance layer (130) exterior to the carbon coating and a metal layer (140) exterior to the low contact resistance layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Linda Shekhawat, Nachiket Raravikar
  • Patent number: 9068067
    Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 30, 2015
    Assignee: INTEL CORPORATION
    Inventors: Dingying Xu, Nisha Ananthakrishnan, Hong Dong, Rahul N. Manepalli, Nachiket Raravikar, Gregory S. Constable
  • Publication number: 20130341787
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Application
    Filed: December 3, 2012
    Publication date: December 26, 2013
    Inventors: Nachiket Raravikar, Dawwoong Suh
  • Patent number: 8558218
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Patent number: 8530890
    Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Ravindra Tanikella
  • Publication number: 20130216828
    Abstract: A thermally and electrically conductive structure comprises a carbon nanotube (110) having an outer surface (111) and a carbon coating (120) covering at least a portion of the outer surface of the carbon nanotube. The carbon coating may be applied to the carbon nanotube by providing a nitrile-containing polymer, coating the carbon nanotube with the nitrile-containing polymer, and pyrolyzing the nitrile-containing polymer in order to form the carbon coating on the carbon nanotube. The carbon nanotube may further be coated with a low contact resistance layer (130) exterior to the carbon coating and a metal layer (140) exterior to the low contact resistance layer.
    Type: Application
    Filed: March 28, 2013
    Publication date: August 22, 2013
    Inventors: Linda Shekhawat, Nachiket Raravikar
  • Patent number: 8344483
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh
  • Publication number: 20120270008
    Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 25, 2012
    Applicant: Intel Corporation
    Inventors: Nachiket Raravikar, Ravindra Tanikella
  • Patent number: 8222750
    Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Ravindra Tanikella
  • Publication number: 20120148842
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 14, 2012
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Patent number: 8158968
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: April 17, 2012
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Publication number: 20120074597
    Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Dingying Xu, Nisha Ananthakrishnan, Hong Dong, Rahul N. Manepalli, Nachiket Raravikar, Gregory S. Constable
  • Publication number: 20120050940
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 1, 2012
    Inventors: Nachiket Raravikar, Rahul Panat
  • Publication number: 20110278351
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein a magnetic particle attachment material comprising magnetic particles distributed within a carrier material may be used to achieve attachment between microelectronic components. The magnetic particle attachment material may be exposed to a magnetic field, which, through the vibration of the magnetic particles within the magnetic particle attachment material, can heat a solder material to a reflow temperature for attaching microelectronic components of the microelectronic packages.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 17, 2011
    Inventors: Aleksandar Aleksov, Rajasekaran Swaminathan, Nachiket Raravikar
  • Publication number: 20100219511
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Application
    Filed: May 11, 2010
    Publication date: September 2, 2010
    Inventors: Nachiket Raravikar, Daewoong Suh