Abstract: A metrology system may include an optical metrology sub-system to generate optical metrology measurements of optical metrology based on features of the optical metrology targets associated with at least one optical pitch and an additional metrology sub-system to generate additional metrology measurements of the optical metrology targets, where the additional metrology measurements have a higher resolution than the optical metrology measurements, and where the additional metrology sub-system further measures deviations of the optical metrology targets from a reference design. The system may further include a controller to generate accuracy measurements for the optical metrology targets based on the measurements, identify variations of a lithography process based on the deviations, correlate the accuracy measurements to the variations, and adjust at least one of the optical metrology sub-system, a lithography tool, or the reference design based on the correlations.

Abstract: A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.

Abstract: A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.

Abstract: A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.