Patents by Inventor Nadav Levison
Nadav Levison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230314508Abstract: Embodiments of apparatuses and methods for in-field testing of an integrated circuit (IC) are disclosed. In an embodiment, an apparatus includes an IC having circuitry to operate in a structural test mode, the structural test mode including a memory built-in self-test (MBIST) mechanism and an automatic test pattern generation (ATPG) mechanism; a microcontroller to enable and control the structural test mode during in-field operation of the IC; and a programmable logic device to support the ATPG mechanism.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Elik Haran, Nir Gerber, Tal Davidson, Wei Hu, Nadav Levison
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Publication number: 20180157492Abstract: A processor includes a hardware-implemented pipeline and parallelization circuitry. The pipeline processes program code. The parallelization circuitry creates a first (earlier) segment and a second (later) segment of the program code to be processed in parallel. Each segment is an ordered sequence of instructions within the program code. A last store to a memory address is identified in the first segment. During parallelized processing of the first segment and the second segment, the parallelization circuitry controls second segment loads which are potentially dependent on the last store by: during processing of the first segment instructions, providing a release notification when the memory address is available for subsequent instructions, and, during processing of the second segment instructions, issuing a second segment load which is potentially dependent on the last store for execution after the release notification is provided.Type: ApplicationFiled: December 1, 2016Publication date: June 7, 2018Inventors: Nadav LEVISON, Noam MIZRAHI
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Publication number: 20180129501Abstract: Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. The pair of micro-operations includes a first micro-operation for performing a first function and a non-consecutive second micro-operation for performing a second function. The first micro-operation precedes the second micro-operation in the sequence of micro-operations being processed. The first micro-operation is merged into the second micro-operation to create a third micro-operation which performs both the first function and the second function. In up/down fusion the third micro-operation is dispatched instead of the first micro-operation or instead of the second micro-operation, based on whether fuse-up or fuse-down is performed.Type: ApplicationFiled: August 30, 2017Publication date: May 10, 2018Inventors: Nadav LEVISON, Noam MIZRAHI, Jonathan FRIEDMANN
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Publication number: 20180129498Abstract: Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. The pair of micro-operations includes a first micro-operation for performing a first function and a non-consecutive second micro-operation for performing a second function. The first micro-operation precedes the second micro-operation in the sequence of micro-operations being processed. The first micro-operation is merged into the second micro-operation to create a third micro-operation which performs both the first function and the second function. In up/down fusion the third micro-operation is dispatched instead of the first micro-operation or instead of the second micro-operation, based on whether fuse-up or fuse-down is performed.Type: ApplicationFiled: August 30, 2017Publication date: May 10, 2018Inventors: Nadav LEVISON, Noam Mizrahi, Jonathan Friedmann
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Patent number: 9298460Abstract: Systems and methods are disclosed for enhancing the throughput of a processor by minimizing the number of transfers of data associated with data transfer between a register file and a memory stack. The register file used by a processor running an application is partitioned into a number of blocks. A subset of the blocks of the register file is defined in an application binary interface enabling the subset to be pre-allocated and exposed to the application binary interface. Optionally, blocks other than the subset are not exposed to the application binary interface so that the data relating to application function switch or a context switch is not transferred between the unexposed blocks and a memory stack.Type: GrantFiled: November 29, 2011Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Revital Eres, Amit Golander, Nadav Levison, Sagi Manole, Ayal Zaks
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Patent number: 8850095Abstract: A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).Type: GrantFiled: February 8, 2011Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Amit Golander, Omer Heymann, Nadav Levison, Eric F. Robinson
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Publication number: 20130151818Abstract: A method and system for improving performance and latency of instruction execution within an execution pipeline in a processor. The method includes finding, while decoding an instruction, a pointer register used by the instruction; reading the pointer register; validating a pointer register entry; reading, if the pointer register entry is valid, a register file entry; validating a register file entry; validating, if the register file entry is invalid, a valid register file entry wherein the valid register file entry is in the register file's future file; bypassing, if the valid register file entry is valid, a valid register file value from the register file's future file to the execution pipeline wherein the valid register file value is in the valid register file entry; and executing the instruction using the valid register file value; wherein at least one of the steps is carried out using a computer device.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: International Business Machines CorporationInventors: Erez Barak, Alejandro Rico Carro, Jeffrey H. Derby, Amit Golander, Omer Heymann, Nadav Levison, Sagi Manole, Robert K. Montoye
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Publication number: 20130138922Abstract: Systems and methods are disclosed for enhancing the throughput of a processor by minimizing the number of transfers of data associated with data transfer between a register file and a memory stack. The register file used by a processor running an application is partitioned into a number of blocks. A subset of the blocks of the register file is defined in an application binary interface enabling the subset to be pre-allocated and exposed to the application binary interface. Optionally, blocks other than the subset are not exposed to the application binary interface so that the data relating to application function switch or a context switch is not transferred between the unexposed blocks and a memory stack.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: International Business Machines CorporationInventors: Revital Eres, Amit Golander, Nadav Levison, Sagi Manole, Ayal Zaks
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Patent number: 8352646Abstract: Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.Type: GrantFiled: December 16, 2010Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Jason A. Cox, Omer Heymann, Nadav Levison, Kevin C. Lin, Eric F. Robinson
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Publication number: 20120203946Abstract: A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).Type: ApplicationFiled: February 8, 2011Publication date: August 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Amit Golander, Omer Heymann, Nadav Levison, Eric F. Robinson
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Publication number: 20120159082Abstract: Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.Type: ApplicationFiled: December 16, 2010Publication date: June 21, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason A. Cox, Omer Heymann, Nadav Levison, Kevin C. Lin, Eric F. Robinson