Patents by Inventor Nadeem Fahmi

Nadeem Fahmi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for flexible physical layout in a heterogeneous configurable integrated circuit
    Patent number: 7719449
    Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: May 18, 2010
    Assignee: Agate Logic, Inc.
    Inventors: Nadeem Fahmi, Jason Alexander Jones
  • SYSTEM AND METHOD FOR FLEXIBLE PHYSICAL LAYOUT IN A HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT
    Publication number: 20100045493
    Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on
    Type: Application
    Filed: August 21, 2008
    Publication date: February 25, 2010
    Applicant: CSWITCH CORPORATION
    Inventors: Nadeem Fahmi, Jason Alexander Jones