Abstract: A coverage analysis process and apparatus assigns a unique label for every unique cycle of data produced by simulation or testing. The labels are substituted for the signal evaluations producing a graph of labels over time. The coverage analysis then generates a function, which represents the graph and the function is stored. The functions are analyzed and compared to determine coverage information. The coverage analysis process and apparatus provides significant data compression and represents the coverage in a form, which can easily be analyzed and compared.

Abstract: A data structure to aid in and a method, system, and computer program product for prefetching data from a data cache are provided. In one embodiment, the data structure includes a prediction history field, a next line address field, and a data field. The prediction history field provides information about the success of past data cache address predictions. The next line address field provides information about the predicted next data cache lines to be accessed. The data field provides data to be used by the processor. When a data line in the data cache is accessed by the processor, determines the value of a prediction history field and the value of a next line address field. If the prediction history field is true, then the next line address in the next line address field is prefetched. Based on whether the next line actually utilized by the processor matches the next line address in the next line address field, the contents of the prediction history field and the next line address filed are modified.

Abstract: A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state.

Abstract: An apparatus and method for providing selective views of on-line surveys are provided. With the apparatus and method, each survey has a survey data structure and a template data structure. In a preferred embodiment, the data structures represent tree structures having nodes, child nodes, links between nodes and child nodes, and the like, for the survey and the template. Changes to the survey are made in the template data structure. The survey data structure and the template data structure are compared to one another, and nodes are either added, subtracted, or modified based on the differences between the survey data structure and the template data structure. In this way, the survey data structure retains the information that is already in present in it, such as the questions and answers previously provided. Thereafter, when the survey is again presented to a user, the user's previous answers to questions still remaining in the survey are displayed but no answers are displayed for newly added questions.

Abstract: A method of database management for distributing data relative to the job performances of short term job contractors comprising soliciting through an interactive computer display interface, job performance evaluations from each of a plurality of employers for each of a plurality of short term job contractors and storing such job performance evaluations. The method and system then interpret the job performance evaluations for each of the job contractors and permit each of said employers to obtain an interpreted job performance evaluation for each of said job contractors. The step of interpreting the evaluation by the third party database manager combines the job performance evaluations from a plurality of said employers for each of said job contractors. In such a case, the individual employers' evaluations are further safeguarded by being integrated with the evaluations of several other businesses. The resulting evaluations are preferably numerical.

Abstract: In one aspect, a method for comparing suppliers includes sending survey questions for receipt by supplier computer systems. Programming instructions are also sent for receipt and execution by the supplier computer systems, The programming instructions are for causing the supplier computer systems to return supplier survey answers to a server. The answers are included in responding documents and are defined in a certain format as data elements included in the responding documents. The data elements are then parsed from the responding documents responsive to predetermined programming instructions and evaluated the data elements responsive to a predetermined set of rules.

Abstract: A survey document is provided on a server, for delivery to a client on a network, having questions and potential answers in a format defining branches of the questions. Programming instructions are also provided on the server for delivery to the client on the network. The instructions are for causing the client to render questions on a user interface from the survey document. The questions initially rendered include a first one of the questions. The instructions are also for causing the client to branch to and render on the user interface second or third ones of the questions responsive to the survey document and an answer received for the first question.

Abstract: A high performance voice transformation apparatus and method is provided in which voice input is transformed into a symbolic representation of phonemes in the voice input. The symbolic representation is used to retrieve output voice segments of a selected target speaker for use in outputting the voice input in a different voice. In addition, voice input characteristics are extracted from the voice input and are then applied to the output voice segments to thereby provide a more realistic human sounding voice output.

Abstract: A method for automatically generating a set of specifications against which a model of the digital circuit can be verified. In one embodiment, the method includes an initial step in which a specification class that corresponds to a type of behavior of the digital circuit is defined. A set of specification formulae that satisfies the defined specification class is then enumerated. Each formula in the set of formulae is then applied to the model of the digital circuit to determine whether the digital circuit satisfies the corresponding formula. The definition of the specification class preferably includes a set of input conditions, a set of output or response conditions, and a temporal component. Preferably, the enumeration of the specification formulae includes all specification formulae that satisfy the specification class. The application of the set of formulae to the model of the digital circuit is preferably achieved with a verification engine such as a model checker.

Abstract: A system and method for compressing data on a computer system is disclosed. The method and system include separating the data into a plurality of segments. The plurality of segments includes a plurality of unique segments. The method and system also include providing a plurality of code words. Each of the plurality of code words corresponds to a unique segment of the plurality of unique segments. The method and system also include providing a representation of the data. The representation includes the plurality of code words for the plurality of segments. The plurality of code words in the representation replaces the plurality of segments. As a result, the data in the representation could be accessed randomly.

Abstract: An apparatus and method for compressing pseudo-random data is provided. The apparatus and method make use of stochastic distribution models to generate approximations of the input data. A data sequence obtained from the stochastic distribution models is compared to the input data sequence to generate a difference data sequence. The difference data sequence tends to be less “random” than the input data sequence and is thus, a candidate for compression using pattern repetition. The difference data sequence is compressed using standard compression techniques and stored as a compressed data file along with information identifying the stochastic distribution model used and any parameters of the stochastic distribution model, including seed value and the like. When decompressing a data file compressed in the manner described above, the compressed difference data sequence is decompressed and a data sequence is generated using the identified stochastic distribution model and model parameters.

Abstract: A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.

Abstract: A method and apparatus in a data processing system for manipulating a set of binary decision diagrams. A plurality of segments is created from the set of binary decision diagrams. A group of compression codes is associated with the set of segments, wherein the group of compression codes form a compressed data structure representing the set of binary decision diagrams.

Abstract: A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-sector basis) rather than renaming an entire processor register. A register is divided into sectors such that the smallest accessible unit for an instruction in each register can be uniquely addressed and renamed. A register file is divided into sectors so that each process register can be uniquely addressed and renamed. The most significant sectors of the processor registers are used to hold pre-assigned values therein. Data previously loaded into processor register sectors is stored in the most significant sectors of the processor registers for possible future referencing and use. The method also includes establishing a sign-extend memory that includes at least one sign-extend bit in a sector status table.

Abstract: A system and method for compressing state transition data on a computer system is disclosed. The method and system include separating the state transition data into a plurality of segments and separating each of the plurality of segments into a plurality of subsegments. The method and system further include providing a plurality of code words. Each of the plurality of code words corresponds to a unique subsegment of the plurality of unique subsegments. The method and system also include providing a representation of each segment. The representation of each segment includes a portion of the plurality of code words. The portion of the plurality of code words replaces the plurality of subsegments in each of the plurality of segments. Thus, the present invention allows compressed state transition data to be used without full uncompression, allowing a system to be explicitly checked without substantial loss of information and without consuming memory.

Abstract: A method for compressing files utilizing a dictionary within a data-processing system is disclosed. A binary file commonly available to a data-compressing system during compression and to a data-decompressing system during decompression can be served as a dictionary file. A first dictionary array is initially generated utilizing the dictionary file. Each entry within the first dictionary array includes a set of unique bit patterns from the dictionary file. An input file is parsed into multiple blocks, with each block having the same length as each entry within the first dictionary array. The input file is then compared against the first dictionary array, and each entry within the first dictionary array that includes the same bit patterns as a block from the input file is marked accordingly. A second dictionary array that includes all the marked entries from the first dictionary array is subsequently generated, and this second dictionary array is utilized in the compression of the input file.

Abstract: A method is provided for automatically enhancing verification of a design under test by using model checking on the state transitions captured during simulation. The enhanced verification is due to the fact that even though to all of the individual transitions captured were exercised during simulation, not all possible sequences of those transitions were necessarily exercised during the simulation, and the unexercised sequences may hide "bugs". The non-deterministic and exhaustive nature of the model checker ensures that all possible sequences comprising the captured state transitions are exercised. The methodology consists of utilizing the state transitions, and the inputs causing those state transitions as observed during simulation, to define legitimate input values that can be applied, nondeterministically and exhaustively, by the model checker to the design under test.

Abstract: The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof.

Abstract: A method and implementing computer system is provided in which an internet or web network user may invoke a hyperlink or site link listing mode to retrieve only the hyperlinks available on selected target pages rather than retrieving the entire text and graphics of the target pages. The network assembles only the available hyperlinks and associated activation code segments for presentation to the user. The user may then select from the presented hyperlinks, the most appropriate hyperlink or path in pursuit of the user's particular search goals. The hyperlink access methodology enables faster navigation through selected and more direct paths to particular search goals by selectively assembling and displaying listings of only hyperlinks of designated target pages rather than entire page presentations.

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.