Abstract: Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. In designs susceptible to post-manufacture data dependent creep in a device characteristic, such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch. Typically, the techniques described herein may be employed to address sensing offsets that have developed post-manufacture due to a data-dependent effect. However, in some realizations, the techniques described herein may be used to address a sensing offset arising at least in part from other or additional sources.

Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured to store the predetermined values on the nodes of the memory array in response to successive enablement of word lines corresponding to the nodes of the memory array and automatic reset of the word lines. Circuitry included for initializing control and data signals of the memory array are effectively disabled upon termination of the initialization. Inclusion of circuitry that initiates and terminates the initialization obviates an additional input/output pin for this purpose.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

Abstract: Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. Such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, purposefully skewed values (e.g., value and value_1) are introduced directly into the sense amplifier. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch.

Abstract: The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. Commonly assigned patent application Ser. No. 10/292329 entitled “On-Chip Measurement of Signal State Duration”, describes examples of a signal state duration measurement system technology that measures signal state durations using on-chip technology. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal.

Abstract: Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (Vt) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominant value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related Vt shift, while the opposing PMOS device will accumulate little or no shift.

Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: In some embodiments, the present application describes an on-chip system and method of determining the effective locked frequency of a PLL. The locked frequency of the PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determined whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal match the jitter in the locked frequency of the PLL, the respective delay of the test signal is used to determine the effective locked frequency of the PLL.

Abstract: Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (Vt) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominant value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related Vt shift, while the opposing PMOS device will accumulate little or no shift.

Abstract: According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a negative bias temperature instability (NBTI) effect on the amplifier.

Abstract: A track ball control system which is attachable to a computer system that has a display screen on which a cursor is positionable, including at least one track ball regulator for providing physical control of the position of the track ball in response to signals from the control system. These signals depend on the location of the cursor on the display screen and cause the track ball to change in movement. This change in movement may be a vertical change, and/or an azimuthal change. The operator does not control this change in movement except indirectly by knowingly or unknowingly positioning the cursor in a position which causes the signals to be sent to the track ball.