Abstract: An apparatus and method for improving the reliability of floating gate transistors used in memory cell applications by controlling the electric field induced across the tunnel oxide region of the floating gate transistor when discharging electrons from floating gate is provided. The invention comprises method and apparatus for varying the resistance applied to the drain electrode of the floating gate device and/or varying the voltage applied to the source electrode of the floating gate device to control the electric field in the tunnel oxide region of the floating gate device. In the preferred embodiment of the invention utilized in an EEPROM memory cell, both a method and an apparatus applying a variable resistance and a method and an apparatus applying a variable voltage are utilized simultaneously. The method and apparatus provide an optimal electric field intensity to control electron tunneling in the tunnel region of the floating gate device during discharge of electrons from the floating gate.

Abstract: A non-volatile memory apparatus having a plurality of memory cells, each memory cell including a floating gate tunnel device (130) having a drain (134) and a floating gate read transistor (140) having a source (142) and a drain (144), the tunnel device and read transistor in each respective cell having a common floating gate (138, 148) and a common control gate (136, 146).

Abstract: A four device cell for an electrically erasable programmable logic device includes a floating gate tunnel device (sometimes referred to as a tunnel capacitor), a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg. V.sub.

Abstract: A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor, a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg .multidot.V.sub.