Abstract: An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Abstract: A sensor device for analyzing fluidic samples is provided. The sensor device includes a stacked sensing arrangement having at least three sensing layers and a multilayer structure. The multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole.

Abstract: A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors are formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).

Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.

Abstract: An electrode for an ionization chamber and an ionization chamber including an electrode are provided wherein the electrode comprises a substrate comprising a first material, and a plurality of nanowires extending from the substrate and manufactured by processing the first material of the substrate.

Abstract: A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed.

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract: A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors arc formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).

Abstract: An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Abstract: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.

Abstract: A sensor device for analyzing fluidic samples is provided, wherein the sensor device comprises a stacked sensing arrangement comprising at least three sensing layers and a multilayer structure, wherein the multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and wherein the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole.

Abstract: A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed.

Abstract: An electrode for an ionization chamber and an ionization chamber including an electrode are provided wherein the electrode comprises a substrate comprising a first material, and a plurality of nanowires extending from the substrate and manufactured by processing the first material of the substrate.

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract: A memory cell (300, 500), the memory cell (300, 500) comprising a substrate (301), a nanowire (302) extending along a vertical trench formed in the substrate (301), a control gate (303) surrounding the nanowire (302), and a charge storage structure (320, 501) formed between the control gate (303) and the nanowire (302).

Abstract: The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-VT state to a low-VT state.

Abstract: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.