Abstract: A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU) cache. The computer system contains an I/O bus connected to I/O devices and an expansion bus connected to expansion memory devices, a system memory not accessible via the I/O bus or expansion bus, and the system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory. The I/O bus supports data transfers between pairs of I/O devices, and I/O devices and expansion memory devices on the expansion bus, as well as data transfers between individual I/O devices and the system, which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device or expansion memory device to a cacheable memory location in another I/O device or expansion memory device.

Abstract: A computer system is provided, comprising system memory and a memory controller which resides on a system bus for controlling access to the system memory, a bus interface unit and a direct memory access controller also residing on the system bus, and a central processing unit electrically connected with the memory controller which is able to read and write data to the system memory via the memory controller. The memory controller and the bus interface unit each operate, when either is in control of the system bus, at a clock frequency which is a multiple of the clock frequency at which the direct memory access controller operates on the system bus. The memory controller and the bus interface unit each operate, when the direct memory access controller is in control of the system bus, at the same clock frequency as that of the direct memory access controller. The clock frequencies of the memory controller, the bus interface unit and the direct memory access controller are each synchronized in time.

Abstract: In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not directly accessible via the I/O bus, and a system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory, a method and apparatus are provided to allow addressable memory locations in both the system memory and I/O devices coupled to the I/O bus to be cacheable in the CPU cache. The I/O bus supports data transfers between pairs of I/O devices, as well as data transfers between individual I/O devices and the system which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device to a cacheable memory location in another I/O device.

Abstract: A bus interface unit for passing data between an I/O bus and a system bus in a dual bus computer system is provided. The bus interface unit has incorporated therein an address listing and compare function to determine whether a requesting device on the I/O bus is to read data from or write data to an address on the system bus. If so, the bus interface unit allows passing of the data therethrough. If not, the system bus is relinquished and the requesting device writes to the address on the I/O bus. Also, compare logic is incorporated in the bus interface unit which decodes system bus addresses originated from a system bus controller such as the DMA, to determine whether the destination of the transfer is to system memory or the I/O bus.

Abstract: A method and system are provided for controlling data transfer between a system memory connected to a system bus and at least one input/output (I/O) device connected to an I/O bus in a computer system. The system bus is coupled to the I/O bus by a bus interface unit comprising a first pair of buffers connected in series between the I/O bus and the system bus, and a second pair of buffers connected in series between the I/O bus and the system bus and in parallel with the first pair of buffers. Each of the buffers in each of the pairs is used for bidirectional data transfer between the system bus and the I/O bus.

Abstract: A device and method for power management of direct memory access ("DMA") slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ("PMM") to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ("CPU") while keeping the disable control signal asserted, which effectively disables the DMA channel.

Abstract: A method and system for improving bus-to-bus data transfers in a multi-bus computer system is provided. The system includes a system bus having a slave device attached thereto, a peripheral bus having a master device attached thereto, and a host bridge connecting the two buses. The system bus permits burst read transfers of data stored in the slave device, wherein a single address phase is followed by several data phases, but only if the first address corresponds to a prescribed system bus boundary. The peripheral bus is not subject to address boundary limitations, instead permitting burst read transfers beginning at any address. The host bridge includes logic for decoding a first address asserted by the master device to determine if it corresponds to a system bus boundary.

Abstract: Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

Abstract: An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.

Abstract: A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.

Abstract: An information handling systems capable of transferring data among various system resource devices such as input/output (I/O) devices and a system memory includes a first bus coupled to the system memory, a second bus coupled to the system resource devices, and a bus interface unit (BIU) coupled between the first bus and the second bus. Each of the system resource devices is capable of controlling the second bus after arbitrating therefor. The BIU includes a buffer for temporary storage of data being transferred between the first bus and the second bus, and control logic for generating a lock control signal, after one of the system resource devices has gained control of the second bus by arbitration, to gain control of the first bus to prevent other system resource devices from accessing the first bus. The control signal is dynamically generated by the BIU based on programmable conditions relating to the data transfer, thus optimizing data transfers between the first bus and the second bus.

Abstract: The present invention provides a program that creates a preliminary map of a multiple bus network used to connect peripheral devices to the central processing unit of an information handling system. This preliminary map is then used by configuration software of the information handling system to locate the peripheral devices in the multiple bus network to configure them. If the physical configuration of the multiple bus network should change in any way, the inventive program can make corresponding changes in the preliminary map without having to rewrite or change the program.

Abstract: Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

Abstract: An information processing system, comprising a central processing unit (CPU); a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; a second system bus connected to the CPU; a host bridge connecting the second system bus to a peripheral bus having at least one peripheral device attached thereto, the host bridge including register space for storing information related to transactions occurring over the peripheral bus; and error capture logic incorporated into the host bridge. The error capture logic monitors the transactions occurring over the peripheral bus, detects parity errors occurring during any of the transactions, and generates an interrupt routine over the second system bus to the CPU. The CPU reads the register space and performs necessary recovery operations.

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus.

Abstract: A device for generating back-to-back data transfers on a bus in an information handling system. A detector for determining whether a first address value and a second address are within a range, a first register connected to the detector for storing the first address until the device generates the second address, a second register connected to the detector for storing the range value, and a transfer state block for driving the second address on the peripheral bus without a turnaround cycle if the detector determines that the first and second addresses are within the range. Thus, back-to-back data transfers are provided.

Abstract: An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto.

Abstract: A direct memory access (DMA) controller for exchanging data information between a system memory and an input/output (I/O) device in an initial data exchange mode and an alternate data exchange mode includes a register for exchanging the data information during both modes and a residual data register for storing residual data information in the register upon commencement of the alternate data exchange mode and for providing the residual data information when the initial data exchange mode is restarted.

Abstract: A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.

Abstract: In a computer system having a CPU and several buses which includes a system bus and an I/O bus, parity error can occur when data is being written between the I/O bus and the system bus. This invention provides a technique for detecting whether a parity error has occurred on data being written between the system bus and the I/O bus. If a parity error is detected, the address at which such error occurred is stored and then sent on to the system bus to the CPU.