Patents by Inventor Nader J. Haddad

Nader J. Haddad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Calibrating a wire load model for an integrated circuit
    Patent number: 7149991
    Abstract: A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: December 12, 2006
    Assignee: NEC Electronics America, Inc.
    Inventors: Attila Kovacs-Birkas, Wolfgang Roethig, Nader J. Haddad
  • Calibrating a wire load model for an integrated circuit
    Publication number: 20040205683
    Abstract: A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.
    Type: Application
    Filed: May 30, 2002
    Publication date: October 14, 2004
    Inventors: Attila Kovacs-Birkas, Wolfgang Roethig, Nader J. Haddad