Patents by Inventor Nader N. Abazarnia
Nader N. Abazarnia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10424559Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.Type: GrantFiled: December 22, 2016Date of Patent: September 24, 2019Assignee: Intel CorporationInventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff
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Patent number: 10281521Abstract: Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.Type: GrantFiled: December 2, 2016Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: David Won-jun Song, James R. Hastings, Akhilesh P. Rallabandi, Morten S. Jensen, Christopher Wade Ackerman, Christopher R. Schroeder, Nader N. Abazarnia, John C. Johnson
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Patent number: 10261121Abstract: Embodiments of the present disclosure describe semiconductor equipment devices having a metal workpiece and a diamond-like carbon (DLC) coating disposed on a surface of the metal workpiece, thermal semiconductor test pedestals having a metal plate and a DLC coating disposed on a surface of the metal plate, techniques for fabricating thermal semiconductor test pedestals with DLC coatings, and associated configurations. A thermal semiconductor test pedestal may include a metal plate and a DLC coating disposed on a surface of the metal plate. The metal plate may include a metal block formed of a first metal and a metal coating layer formed of a second metal between the metal block and the DLC coating. An adhesion strength promoter layer may be disposed between the metal coating layer and the DLC coating. Other embodiments may be described and/or claimed.Type: GrantFiled: May 26, 2016Date of Patent: April 16, 2019Assignee: Intel CorporationInventors: Jelena Culic-Viskota, Nader N. Abazarnia
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Patent number: 10228418Abstract: Embodiments of alignment fixtures for integrated circuit (IC) packages, and related techniques, are disclosed herein. In some embodiments, an alignment fixture for an IC package may include: a first socket having a recess dimensioned to receive a first surface of the IC package and having a first magnet arrangement disposed outside of the recess, wherein the IC package has a second surface opposite to the first surface and has a first electrical contact element on the second surface; and a second socket having a second electrical contact element and having a second magnet arrangement. The first and second electrical contact elements may be aligned when the IC package is disposed in the recess, the IC package is disposed between the first and second sockets, and the first magnet arrangement is in a predetermined equilibrium relation with the second magnet arrangement to mate the first and second sockets.Type: GrantFiled: April 21, 2014Date of Patent: March 12, 2019Assignee: INTEL CORPORATIONInventors: Sruti Chigullapalli, Rene J. Sanchez, Nader N. Abazarnia, Todd R. Coons, Tuan Hoong Goh
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Publication number: 20180182736Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff
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Publication number: 20180156863Abstract: Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.Type: ApplicationFiled: December 2, 2016Publication date: June 7, 2018Inventors: David Won-jun Song, James R. Hastings, Akhilesh P. Rallabandi, Morten S. Jensen, Christopher Wade Ackerman, Christopher R. Schroeder, Nader N. Abazarnia, John C. Johnson
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Publication number: 20170343599Abstract: Embodiments of the present disclosure describe semiconductor equipment devices having a metal workpiece and a diamond-like carbon (DLC) coating disposed on a surface of the metal workpiece, thermal semiconductor test pedestals having a metal plate and a DLC coating disposed on a surface of the metal plate, techniques for fabricating thermal semiconductor test pedestals with DLC coatings, and associated configurations. A thermal semiconductor test pedestal may include a metal plate and a DLC coating disposed on a surface of the metal plate. The metal plate may include a metal block formed of a first metal and a metal coating layer formed of a second metal between the metal block and the DLC coating. An adhesion strength promoter layer may be disposed between the metal coating layer and the DLC coating. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 26, 2016Publication date: November 30, 2017Inventors: Jelena Culic-Viskota, Nader N. Abazarnia
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Publication number: 20170123001Abstract: Embodiments of alignment fixtures for integrated circuit (IC) packages, and related techniques, are disclosed herein. In some embodiments, an alignment fixture for an IC package may include: a first socket having a recess dimensioned to receive a first surface of the IC package and having a first magnet arrangement disposed outside of the recess, wherein the IC package has a second surface opposite to the first surface and has a first electrical contact element on the second surface; and a second socket having a second electrical contact element and having a second magnet arrangement. The first and second electrical contact elements may be aligned when the IC package is disposed in the recess, the IC package is disposed between the first and second sockets, and the first magnet arrangement is in a predetermined equilibrium relation with the second magnet arrangement to mate the first and second sockets.Type: ApplicationFiled: April 21, 2014Publication date: May 4, 2017Inventors: Sruti CHIGULLAPALLI, Rene J. SANCHEZ, Nader N. ABAZARNIA, Todd R. COONS, Tuan Hoong GOH
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Patent number: 9638747Abstract: Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.Type: GrantFiled: December 27, 2013Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Paul J. Diglio, Nader N. Abazarnia, Christopher R. Schroeder, Rene J. Sanchez, Morten S. Jensen
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Publication number: 20150185281Abstract: Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Paul J. Diglio, Nader N. Abazarnia, Christopher R. Schroeder, Rene J. Sanchez, Morten S. Jensen
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Patent number: 8410802Abstract: Systems and methods including testing of electronic components are described. One system relates to a system including a thermal control unit adapted to control the temperature of at least a portion of an electronic component during testing. The system includes at least one conduit extending through a portion of the thermal control unit, the conduit sized to permit the flow of a thermal interface material therethrough, the thermal interface material comprising a liquid. The at least one conduit is positioned so that the thermal interface material can be delivered through the conduit and onto the electronic component. The system also includes a device adapted to control the flow of the thermal interface material through the conduit, wherein the flow can be controlled to deliver the thermal interface material to the electronic component and to remove the thermal interface material from the electronic component. Other embodiments are described and claimed.Type: GrantFiled: December 24, 2009Date of Patent: April 2, 2013Assignee: Intel CorporationInventors: Ashish Gupta, James R. Hastings, Nader N. Abazarnia, Suzana Prstic, Jerome L. Garcia
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Publication number: 20110155348Abstract: Systems and methods including testing of electronic components are described. One system relates to a system including a thermal control unit adapted to control the temperature of at least a portion of an electronic component during testing. The system includes at least one conduit extending through a portion of the thermal control unit, the conduit sized to permit the flow of a thermal interface material therethrough, the thermal interface material comprising a liquid. The at least one conduit is positioned so that the thermal interface material can be delivered through the conduit and onto the electronic component. The system also includes a device adapted to control the flow of the thermal interface material through the conduit, wherein the flow can be controlled to deliver the thermal interface material to the electronic component and to remove the thermal interface material from the electronic component. Other embodiments are described and claimed.Type: ApplicationFiled: December 24, 2009Publication date: June 30, 2011Inventors: Ashish GUPTA, James R. Hastings, Nader N. Abazarnia, Suzana Prstic, Jerome L. Garcia
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Patent number: 6898852Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.Type: GrantFiled: August 25, 2003Date of Patent: May 31, 2005Assignee: Intel CorporationInventors: Nader N. Abazarnia, Jeffrey H. Luke, James Neeb
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Patent number: 6819130Abstract: A floating and self-aligning suspension system to automatically align and attach a connector to an assembly is disclosed. The floating and self-aligning suspension system includes a frame and a biasing mechanism attached to the frame. A connector is mounted to the frame and the biasing mechanism permits the frame and connector to move relative to another structure to allow the connector to self-align and attach to an assembly.Type: GrantFiled: May 15, 2001Date of Patent: November 16, 2004Assignee: Intel CorporationInventors: Nader N. Abazarnia, Jeffrey H. Luke, Nader Shahriari
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Patent number: 6621287Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.Type: GrantFiled: May 15, 2001Date of Patent: September 16, 2003Assignee: Intel CorporationInventors: Nader N. Abazarnia, Jeffrey H. Luke, James Neeb
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Publication number: 20020171444Abstract: A floating and self-aligning suspension system to automatically align and attach a connector to an assembly is disclosed. The floating and self-aligning suspension system includes a frame and a biasing mechanism attached to the frame. A connector is mounted to the frame and the biasing mechanism permits the frame and connector to move relative to another structure to allow the connector to self-align and attach to an assembly.Type: ApplicationFiled: May 15, 2001Publication date: November 21, 2002Applicant: Intel CorporationInventors: Nader N. Abazarnia, Jeffrey H. Luke, Nader Shahriari
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Publication number: 20020171443Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.Type: ApplicationFiled: May 15, 2001Publication date: November 21, 2002Applicant: Intel CorporationInventors: Nader N. Abazarnia, Jeffrey H. Luke, James Neeb