Patents by Inventor Nader Salessi
Nader Salessi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080253199Abstract: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.Type: ApplicationFiled: May 16, 2008Publication date: October 16, 2008Applicant: STEC, INC.Inventors: Hooshmand Torabi, Chak-Fai Cheng, Nader Salessi, Hosein Gazeri
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Publication number: 20080140945Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data addressing is distributed amongst channels to improve system performance and durability. In one embodiment, each channel has an address translation table or address map which is utilized to gain performance improvement during data transfer or erasure, and an increase of the device's useful life span.Type: ApplicationFiled: October 26, 2007Publication date: June 12, 2008Applicant: STEC, Inc.Inventors: Nader Salessi, Hooshmand Torabi
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Publication number: 20080140883Abstract: A process of data storage utilizing a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data management system receives data from the host system and writes the data as data segments to the multiple storage devices. Each data segment may comprise one sector, more than one sector, or a portion of a sector, depending on the embodiment. The data segments are transferred to and from the multiple storage devices in parallel fashion while the data in each data segment is transferred to its corresponding data storage device sequentially. The data management system reassembles data segments received from the data storage devices and sends the data to the host system.Type: ApplicationFiled: October 26, 2007Publication date: June 12, 2008Applicant: STEC, Inc.Inventors: Nader Salessi, Hooshmand Torabi
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Publication number: 20080140919Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data management system receives data from the host system and writes the data as data segments to the multiple storage devices. Each data segment may comprise one sector, more than one sector, or a portion of a sector, depending on the embodiment. The data segments are transferred to and from the multiple storage devices in parallel fashion while the data in each data segment is transferred to its corresponding data storage device sequentially. The data management system reassembles data segments received from the data storage devices and sends the data to the host system.Type: ApplicationFiled: October 26, 2007Publication date: June 12, 2008Applicant: STEC, Inc.Inventors: Hooshmand Torabi, Nader Salessi
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Patent number: 7376034Abstract: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.Type: GrantFiled: February 22, 2006Date of Patent: May 20, 2008Assignee: STEC, Inc.Inventors: Hooshmand Torabi, Chak-Fai Cheng, Nader Salessi, Hosein Gazeri
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Publication number: 20080065905Abstract: A secure storage device includes a storage medium configured to securely store data received from a host. The storage device further includes a host interface configured to transfer data between the host and the storage device and an encryption engine. The encryption engine is configured to encrypt data received from a host using a key and provide the encrypted data to the storage medium for storage. The encryption engine is further configured to decrypt encrypted data received from the storage medium and provide the data to the host via the host interface. In response to a predetermined condition, the storage device is configured to disable the encryption engine thereby preventing the encrypted data stored thereon from being decrypted.Type: ApplicationFiled: September 13, 2006Publication date: March 13, 2008Applicant: SimpleTech, Inc.Inventor: Nader Salessi
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Publication number: 20070165456Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.Type: ApplicationFiled: January 17, 2007Publication date: July 19, 2007Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hosein Gazeri
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Publication number: 20070140020Abstract: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.Type: ApplicationFiled: February 22, 2006Publication date: June 21, 2007Applicant: SimpleTech, Inc.Inventors: Hooshmand Torabi, Chak-Fai Cheng, Nader Salessi, Hosein Gazeri
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Publication number: 20070101049Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command, by writing a pattern of data to the flash storage unit, such that the flash storage units are purged substantially in parallel with each other.Type: ApplicationFiled: October 17, 2006Publication date: May 3, 2007Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hooshmand Torabi, Chak-Fai Cheng, Hosein Gazeri, Richard Mataya
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Publication number: 20070101048Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other. The purge of the flash storage device is subsequently verified.Type: ApplicationFiled: October 17, 2006Publication date: May 3, 2007Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hooshmand Torabi, Chak-Fai Cheng, Hosein Gazeri, Richard Mataya
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Publication number: 20070091697Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command while allowing the flash storage device to be used subsequent to the purge. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other. Subsequent to the purge, certain control data is reconstructed to allow subsequent use of the flash storage device.Type: ApplicationFiled: October 17, 2006Publication date: April 26, 2007Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hooshmand Torabi, Chak-Fai Cheng, Hosein Gazeri, Richard Mataya
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Publication number: 20070088905Abstract: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other.Type: ApplicationFiled: October 17, 2006Publication date: April 19, 2007Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hooshmand Torabi, Chak-Fai Cheng, Hosein Gazeri, Richard Mataya
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Patent number: 7180777Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.Type: GrantFiled: January 17, 2006Date of Patent: February 20, 2007Assignee: SimpleTech, Inc.Inventors: Nader Salessi, Hosein Gazeri
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Publication number: 20060133178Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.Type: ApplicationFiled: January 17, 2006Publication date: June 22, 2006Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hosein Gazeri
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Patent number: 7020019Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.Type: GrantFiled: August 6, 2004Date of Patent: March 28, 2006Assignee: SimpleTech, Inc.Inventors: Nader Salessi, Hosein Gazeri
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Publication number: 20050259469Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.Type: ApplicationFiled: August 6, 2004Publication date: November 24, 2005Applicant: SimpleTech, Inc.Inventors: Nader Salessi, Hosein Gazeri