Patents by Inventor Nadi R. Itani
Nadi R. Itani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7719595Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.Type: GrantFiled: October 30, 2007Date of Patent: May 18, 2010Assignee: Cirrus Logic, Inc.Inventors: Sandra M. Johnson, Douglas R. Holberg, Nadi R. Itani
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Patent number: 7589766Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.Type: GrantFiled: September 10, 2003Date of Patent: September 15, 2009Assignee: Cirrus Logic, Inc.Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
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Patent number: 7522193Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.Type: GrantFiled: June 7, 2004Date of Patent: April 21, 2009Assignee: Cirrus Logic, Inc.Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
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Patent number: 7391452Abstract: A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system correctably extends the dynamic range of the imager device, subject to offsets providing linearity corrections at predetermined trip points, subject to determined offset values, to ensure that there are no discontinuities in the system transfer function.Type: GrantFiled: March 16, 2004Date of Patent: June 24, 2008Assignee: Cirrus Logic, Inc.Inventor: Nadi R. Itani
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Patent number: 7304679Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.Type: GrantFiled: December 19, 2003Date of Patent: December 4, 2007Assignee: Cirrus Logic, Inc.Inventors: Sandra M. Johnson, Douglas R. Holberg, Nadi R. Itani
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Patent number: 7286176Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module.Type: GrantFiled: April 8, 2004Date of Patent: October 23, 2007Assignee: Cirrus Logic, Inc.Inventors: Douglas R. Holberg, Sandra M. Johnson, Nadi R. Itani, Argos R. Cue
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Publication number: 20040189843Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module.Type: ApplicationFiled: April 8, 2004Publication date: September 30, 2004Applicant: Cirrus Logic, Inc.Inventors: Douglas R. Holberg, Sandra M. Johnson, Nadi R. Itani, Argos R. Cue
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Publication number: 20040179118Abstract: A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system correctably extends the dynamic range of the imager device, subject to offsets providing linearity corrections at predetermined trip points, subject to determined offset values, to ensure that there are no discontinuities in the system transfer function.Type: ApplicationFiled: March 16, 2004Publication date: September 16, 2004Inventor: Nadi R. Itani
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Patent number: 6750906Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.Type: GrantFiled: May 8, 1998Date of Patent: June 15, 2004Assignee: Cirrus Logic, Inc.Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
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Patent number: 6720999Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module.Type: GrantFiled: March 31, 1999Date of Patent: April 13, 2004Assignee: Cirrus Logic, Inc.Inventors: Douglas R. Holberg, Sandra M. Johnson, Nadi R. Itani, Argos R. Cue
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Patent number: 6707492Abstract: A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system correctably extends the dynamic range of the imager device, subject to offsets providing linearity corrections at predetermined trip points, subject to determined offset values, to ensure that there are no discontinuities in the system transfer function.Type: GrantFiled: March 31, 1999Date of Patent: March 16, 2004Assignee: Cirrus Logic, Inc.Inventor: Nadi R. Itani
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Publication number: 20040046875Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.Type: ApplicationFiled: September 10, 2003Publication date: March 11, 2004Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
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Patent number: 6686957Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.Type: GrantFiled: March 31, 1999Date of Patent: February 3, 2004Assignee: Cirrus Logic, Inc.Inventors: Sandra M. Johnson, Douglas R. Holberg, Nadi R. Itani
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Patent number: 6650364Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.Type: GrantFiled: May 8, 1998Date of Patent: November 18, 2003Assignee: Cirrus Logic, Inc.Inventors: Nadi R. Itani, Caiyi Wang, David R. Welland
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Patent number: 6285536Abstract: A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate, transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.Type: GrantFiled: November 3, 1999Date of Patent: September 4, 2001Assignee: Cirrus Logic, Inc.Inventors: Douglas R. Holberg, Nadi R. Itani, David R. Welland
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Patent number: 6252536Abstract: A dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system includes a 2-bit ADC for extending the dynamic range of the imager device, which enhances the dynamic range of a 10 bit ADC to 13 bits.Type: GrantFiled: March 31, 1999Date of Patent: June 26, 2001Assignee: Cirrus Logic, Inc.Inventors: Sandra M. Johnson, Nadi R. Itani
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Patent number: 6038116Abstract: A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.Type: GrantFiled: May 8, 1998Date of Patent: March 14, 2000Assignee: Cirrus Logic, Inc.Inventors: Douglas R. Holberg, Nadi R. Itani, David R. Welland