Abstract: Step coverage in contacts may be improved by forming a tapered hole through a dielectric layer by:a) plasma (RIE) etching through a "contact" mask the dielectric for a depth shorter than the thickness of the layer leaving a residual thickness of dielectric on the bottom of the etch;b) removing the residual masking material;c) conformally depositing a TEOS layer;d) etching the conformally deposited TEOS layer without a mask in (RIE) plasma until exposing the underlying silicon or polysilicon with which the contact must be established.The anisotropic etching of the TEOS layer, conformally deposited on the partially pre-etched dielectric layer, determines a "self-aligned" exposition of the underlying silicon or polysilicon and leaves a tapered TEOS residue on the vertical pre-etched hole's walls, thus providing a desired tapering of the contact hole. Photolithographic definition is no longer a critical factor.

Abstract: Encased (BOX) trench insolation structures in a silicon substrate are formed by firstly RIE etching an ONO multilayer (Oxide-Nitrite-Oxide) formed on the surface of a monocrystalline silicon substrate through a mask defining the active areas until exposing the silicon. A successive deposition of a conformable TEOS oxide layer followed by a "blanket" RIE etching, leave tapered "spacers" on the vertical etched flanks of the ONO multilayer. Through such a self-aligned "aperture" an isotropic plasma etching (round-etch) of the silicon is performed until the lateral, under-cut, etch front below the oxide spacers reaches the bottom layer of the isolation area defining etching previously conducted through the ONO multilayer. The peculiarities of the round-etch profile are thus fully exploited for more easily implanting the walls and bottom of the trench and avoiding the presence of electric field affecting sharp corners.

Abstract: A process for forming self-aligned metal-semiconductor contacts in integrated MISFET devices determining during a phase of the fabrication the presence on the surface of a wafer of parallel gate lines of polycrystalline silicon provided with lateral "spacers", is founded on the formation of a dielectric oxide layer of a differentiated thickness, having a reduced thickness on the bottom of the valley between two adjacent gate lines wherein the contacts must be formed. The method comprises conformably depositing a first layer of dielectric silicon oxide, a second layer of precursor polycrystalline silicon and a third layer of nitride, followed by depositing a layer of planarization SOG. By blanket etching the SOG layer and the nitride layer, the crests of the precursor polycrystalline silicon layer are exposed. A residual layer of nitride is left inside the valley between adjacent gate lines.