Abstract: The gate electrode of a polysilicon gate MOS transistor--the transistor having either a thin film polysilicon substrate or a bulk monocrystalline substrate--has a pair of contiguous regions: a heavily doped gate electrode region near the source, and a lightly doped gate electrode region near the drain. The gate electrode region near the drain is thus doped significantly more lightly, in order to reduce electric fields in the channel region in the neighborhood of the drain (and hence reduce field induced leakage currents) when voltages are applied to turn transistor OFF. At the same time, sufficient impurity doping is introduced into the gate electrode region near the source in order to enable the transistor to turn ON when other suitable voltages are applied.

Abstract: Parallel metallization lines for a substrate of an electronic device, such as complementary bit (B and B) lines for an SRAM cell array, are formed by:forming a uniformly thick aluminum layer with an underlying and overlying dielectric oxide layer, the underlying oxide layer being located overlying the substrate,patterning the overlying oxide and the aluminum layers to form the aluminum bit line (B) with an overlying dielectric oxide layer on its top surface, typically by means of reactive ion etching,depositing a further dielectric oxide layer on the entire surface of the structure including the sidewalls of the aluminum bit line (B), andreactive ion etching the top surface of the oxide layer, whereby an oxide layer remains on the top and sidewall surfaces of the aluminum bit line (B) but not elsewhere.

Abstract: In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas, source region and drain regions; then opening a region for the channel; and finally depositing a layer to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.

Abstract: For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 .mu.m and are made through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completes the contact.

Abstract: The TVS method is a voltammetric method for detecting mobile ionic impurities in the dielectric layer of a MOS capacitor structure. Disclosed here is a method of semiconductor device fabrication involving a modified TVS method in which the voltage is changed in discrete steps rather than varied continuously, and charge, rather than induced current, is measured. The modified TVS method can be faster than conventional TVS, and calibration is unnecessary.

Abstract: Disclosed is a method of semiconductor device fabrication involving the detection of water in a dielectric layer that is part of the body of such device. At relatively high values of a voltage applied across the dielectric layer, water that is present in the dielectric decomposes and releases protons. Varying the applied voltage gives rise to a displacement current. The released protons contribute an ionic component to the displacement current. The ionic component is detected.

Abstract: In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide while doping selected portions of the body. During a subsequent heating step, source, drain and ohmic contact regions are formed in the body. During the same step, the dopant in the metallic silicide diffuses into underlying layers of polysilicon and into body portions directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.

Abstract: In a VLSI device fabrication process, erosion of a patterned resist layer (16, 18) during dry etching of an underlying layer (14) can significantly limit the high-resolution patterning capabilities of the process. As described herein, a protective polymer layer (60, 62) is formed and maintained only on the resist material (16, 18) while the underlying layer (14) is being etched. High etch selectivities are thereby achieved. As a consequence, very thin resist layers can be utilized in the fabrication process and very-high-resolution patterning for VLSI devices is thereby made feasible.