Patents by Inventor Nadia Yala

Nadia Yala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7337528
    Abstract: A textured dielectric patch antenna is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel are metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: March 4, 2008
    Assignee: Motorola, Inc.
    Inventors: Gregory J. Dunn, Jovica Savic, John A. Svigelj, Nadia Yala
  • Patent number: 7265994
    Abstract: A self supported underfill film (18) adhesively bonds surface mount integrated circuit packages (14) to a printed circuit board (10). The printed circuit board has conductive traces (12) and exposed conductive pads (13) on the surface. A film adhesive is strategically positioned on the printed circuit board near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads (16) on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: September 4, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Janice Danvir, Katherine Devanie, Nadia Yala
  • Publication number: 20060137173
    Abstract: A textured dielectric panel (305, 520, 625, 745, 925, 1035, 1205) is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a-second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel may be metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Inventors: Gregory Dunn, Jovica Savic, John Svigelj, Nadia Yala
  • Patent number: 6774497
    Abstract: The invention provides a method for attaching a flip chip to an electrical substrate such as a printed wiring board. A bumped flip chip is provided, the flip chip including an active surface and a plurality of connective bumps extending from the active surface, each connective bump including a side region. A thin layer of an underfill material is applied to the active surface of the flip chip and to a portion of the side regions of the connective bumps. The flip chip is positioned on the electrical substrate, the electrical substrate including a thick layer of a solder mask disposed on the electrical substrate. The flip chip is heated to electrically connect the flip chip to the electrical substrate, wherein the underfill material and the solder mask combine to form a stress-relief layer when the flip chip is electrically connected to the electrical substrate.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: August 10, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jing Qi, Janice M. Danvir, Tomasz L. Klosowiak, Prasanna Kulkarni, Nadia Yala
  • Publication number: 20040150967
    Abstract: A self supported underfill film (18) adhesively bonds surface mount integrated circuit packages (14) to a printed circuit board (10). The printed circuit board has conductive traces (12) and exposed conductive pads (13) on the surface. A film adhesive is strategically positioned on the printed circuit board near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads (16) on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.
    Type: Application
    Filed: January 31, 2003
    Publication date: August 5, 2004
    Inventors: Janice Danvir, Katherine Devanie, Nadia Yala
  • Patent number: 6650022
    Abstract: A bumped semiconductor device (10) exhibiting enhanced pattern recognition when illuminated in a machine vision system. The semiconductor device has a substantially coplanar array of solder bumps (16) and a coating of underfill material (17) on one face. A fluxing composition (18) containing an image enhancing agent is selectively deposited over at least two of the solder bumps in the array to modify the optical characteristics of the solder bumps to cause the solder bumps to appear bright against the background of the underfill material when the semiconductor device is illuminated (19) by selected wavelengths of light.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: November 18, 2003
    Assignee: Motorola, Inc.
    Inventors: Jing Qi, Janice Danvir, Zhaojin Han, Prasanna Kulkarni, Nadia Yala, Robert Doot
  • Publication number: 20030132513
    Abstract: An interposer-based semiconductor package (40) having at least one semiconductor die (21) attached to one side thereof also has, prior to placement on a printed wiring board (61), an underfill material (31) disposed at least partially thereon. Depending upon the embodiment, the underfill material (31) may initially cover interface electrodes (12) on the interposer (11). Such material (31) can be selectively removed to partially expose the interface electrodes (12). In other embodiments, apertures (101) can be left in the underfill material (31) during deposition, or formed after the underfill material (31) has been deposited, and the interface electrodes (12) subsequently formed in the apertures (101). Deposition of the underfill material (31) can be done with a single interposer-based package (40) or simultaneously with a plurality of such packages. Once deposited, the underfill material can be processed to render it relatively stable an substantially non-tacky.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 17, 2003
    Applicant: Motorola, Inc.
    Inventors: Marc Chason, Janice Danvir, Jing Qi, Nadia Yala