Abstract: Devices and methods of a transistor device including a source and a drain, the source and drain are at a horizontal plane at a location along a vertical direction. A gate, that is at a higher horizontal plane along the vertical direction then the source and drain horizontal plane. A first region under the source and drain horizontal plane, includes a first three Nitride (III-N) layer, a second III-N layer over the first III-N layer. A second region under the gate, includes a first III-N layer, a second III-N layer over the first III-N layer, and a third III-N layer over the second III-N layer. The third III-N layer at selective locations extends through the second III-N layer and into a portion of the first III-N layer along a width of the transistor. The third III-N layer is doped P-type, and the first and second III-N layers are unintentionally doped.

Abstract: The present disclosure discloses a negative inductor device. The negative inductor device comprises a negative inductor comprising a ferromagnetic material and a conductive material arranged inside the ferromagnetic material. The negative inductor device further comprises a current limiting circuit electrically coupled to the negative inductor and configured to supply an electric current of magnitude within a range, the range being defined by a first local minimum and a second local minimum of a current-energy curve of the ferromagnetic material.

Abstract: Devices and methods of a field effect transistor device that include a source, a gate and a drain. The transistor includes a semiconductor region position is under the source, the gate and the drain. Such that the semiconductor region can include a gallium nitride (GaN) layer and an III Nitride (III-N) layer. Wherein the GaN layer includes a band gap, and the III-N layer includes a band gap. Such that the III-N layer band gap is higher than the GaN layer band gap. A sub-region of the semiconductor region is located underneath the gate and is doped with Mg ions at selective locations in the sub-region.

Abstract: A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes.

Abstract: Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.

Abstract: Devices and methods of a transistor device including a source and a drain, the source and drain are at a horizontal plane at a location along a vertical direction. A gate, that is at a higher horizontal plane along the vertical direction then the source and drain horizontal plane. A first region under the source and drain horizontal plane, includes a first three Nitride (III-N) layer, a second III-N layer over the first III-N layer. A second region under the gate, includes a first III-N layer, a second III-N layer over the first III-N layer, and a third III-N layer over the second III-N layer. The third III-N layer at selective locations extends through the second III-N layer and into a portion of the first III-N layer along a width of the transistor. The third III-N layer is doped P-type, and the first and second III-N layers are unintentionally doped.

Abstract: Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.

Abstract: Devices and methods of a field effect transistor device that include a source, a gate and a drain. The transistor includes a semiconductor region position is under the source, the gate and the drain. Such that the semiconductor region can include a gallium nitride (GaN) layer and an III Nitride (III-N) layer. Wherein the GaN layer includes a band gap, and the III-N layer includes a band gap. Such that the III-N layer band gap is higher than the GaN layer band gap. A sub-region of the semiconductor region is located underneath the gate and is doped with Mg ions at selective locations in the sub-region.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: A high electron mobility transistor includes a set of electrodes, such as a source, a drain, a top gate, and a side gate, and includes a semiconductor structure having a fin extending between the source and the drain. The top gate is arranged on top of the fin, and the side gate is arranged on a sidewall of the fin at a distance from the top gate. The semiconductor structure includes a cap layer positioned beneath the top gate and a channel layer arranged beneath the cap layer for providing electrical conduction. The cap layer includes nitride-based semiconductor material to enable a heterojunction forming a carrier channel between the source and the drain.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: A high electron mobility transistor (HEMT) includes a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack. The stack of layers includes a first layer and a second layer. The magnitude of polarization of the first layer is greater than the magnitude of polarization of the second layer arranged in the stack below the first layer, and the width of the first layer is less than the width of the second layer to form a staircase profile of the semiconductor structure. The HEMT includes a source semiconductor structure including a heavily doped semiconductor material, a drain semiconductor structure including the heavily doped semiconductor material. The HEMT includes a source, a drain, and a gate electrodes to modulate the conductivity of the carrier channels.

Abstract: A filter includes a circuit including a resistor, a positive capacitor, and a negative capacitor connected in series to accept the same current. The filter also includes an input terminal to accept an input voltage across the circuit and an output terminal to deliver an output voltage taken across the resistor or the positive capacitor.

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor structure including a cap layer and a channel layer forming a heterojunction, such that a two dimensional electron gas is formed at the interface of cap layer and the channel layer. The HEMT also includes a set of electrodes including a source electrode, a drain electrode, and a gate electrode deposited on the cap layer. The gate electrode is arranged between the source and the drain electrode along the length of the HEMT. The thickness of the cap layer at least under the gate electrode is varying along the width of the HEMT.

Abstract: A high electron mobility transistor (HEMT) includes a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack. The stack of layers includes a first layer and a second layer. The magnitude of polarization of the first layer is greater than the magnitude of polarization of the second layer arranged in the stack below the first layer, and the width of the first layer is less than the width of the second layer to form a staircase profile of the semiconductor structure. The HEMT includes a source semiconductor structure including a heavily doped semiconductor material, a drain semiconductor structure including the heavily doped semiconductor material. The HEMT includes a source, a drain, and a gate electrodes to modulate the conductivity of the carrier channels.

Abstract: A high electron mobility transistor includes a semiconductor structure having a channel layer and a cap layer forming a two dimensional electron gas (2-DEG) channel, and a source, a drain, and a gate electrodes. The gate is arranged on the cap layer between the source and the drains, such that the conductivity of the 2-DEG channel is modulated in response to applying voltage to the gate. The cap layer includes III-N material. The gate has a layered structure including a bottom metal layer arranged on cap layer, a ferroelectric oxide (FEO) layer arranged on bottom metal layer, and a top metal layer arranged on the FEO layer. Thickness of FEO layer is less than tcap/(2??cap), wherein ? is a parameter of material of FEO layer, tcap is thickness of cap layer, and ?cap is electric permittivity of cap layer.

Abstract: A high electron mobility transistor (HEMT) includes a semiconductor structure including a cap layer and a channel layer forming a heterojunction, such that a two dimensional electron gas is formed at the interface of cap layer and the channel layer. The HEMT also includes a set of electrodes including a source electrode, a drain electrode, and a gate electrode deposited on the cap layer. The gate electrode is arranged between the source and the drain electrode along the length of the HEMT. The thickness of the cap layer at least under the gate electrode is varying along the width of the HEMT.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: A filter includes a circuit including a resistor, a positive capacitor, and a negative capacitor connected in series to accept the same current. The filter also includes an input terminal to accept an input voltage across the circuit and an output terminal to deliver an output voltage taken across the resistor or the positive capacitor.