Patents by Inventor Nadine Collaert
Nadine Collaert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9601488Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: GrantFiled: April 25, 2016Date of Patent: March 21, 2017Assignee: IMEC VZWInventors: Niamh Waldron, Clement Merckling, Nadine Collaert
-
Publication number: 20160320336Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.Type: ApplicationFiled: April 29, 2016Publication date: November 3, 2016Inventors: Nadine COLLAERT, Voon Yew Thean
-
Publication number: 20160240532Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: ApplicationFiled: April 25, 2016Publication date: August 18, 2016Inventors: Niamh Waldron, Clement Merckling, Nadine Collaert
-
Patent number: 9419110Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.Type: GrantFiled: November 11, 2015Date of Patent: August 16, 2016Assignee: IMEC VZWInventors: Clement Merckling, Nadine Collaert
-
Publication number: 20160141391Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.Type: ApplicationFiled: November 11, 2015Publication date: May 19, 2016Applicant: IMEC VZWInventors: Clement Merckling, Nadine Collaert
-
Publication number: 20160126131Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.Type: ApplicationFiled: October 28, 2015Publication date: May 5, 2016Applicant: IMEC VZWInventors: Nadine Collaert, Geert Eneman, Naoto Horiguchi, Min-Soo Kim, Rita Rooyackers, Anabela Veloso, Liesbeth Witters
-
Patent number: 9324818Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: GrantFiled: March 27, 2015Date of Patent: April 26, 2016Assignee: IMEC VZWInventors: Niamh Waldron, Clement Merckling, Nadine Collaert
-
Patent number: 9257539Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.Type: GrantFiled: December 10, 2014Date of Patent: February 9, 2016Assignee: IMEC VZWInventors: Rita Rooyackers, Nadine Collaert, Geert Eneman
-
Publication number: 20150279947Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: ApplicationFiled: March 27, 2015Publication date: October 1, 2015Inventors: Niamh Waldron, Clement Merckling, Nadine Collaert
-
Publication number: 20150179755Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.Type: ApplicationFiled: December 10, 2014Publication date: June 25, 2015Inventors: Rita Rooyackers, Nadine Collaert, Geert Eneman
-
Publication number: 20130341185Abstract: The present invention relates to a method for fabricating a semiconductor device for stimulation and/or data recording of biological material to a such semiconductor device. The method comprises providing a semiconductor substrate comprising a first insulating layer; providing a patterned conductive layer on top of the first insulating layer; depositing and patterning a second insulating layer atop the patterned conductive layer; growing carbon nano-sheets atop the second insulating layer; and defining carbon nano-sheet electrode areas on the second insulating layer by etching away the carbon nano-sheets outside of the carbon nano-sheet electrode areas.Type: ApplicationFiled: June 12, 2013Publication date: December 26, 2013Inventors: Nadine Collaert, Daire J. Cott, Michael De Volder
-
Patent number: 8445963Abstract: A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.Type: GrantFiled: November 19, 2010Date of Patent: May 21, 2013Assignee: IMECInventors: Stefan Jakschik, Nadine Collaert
-
Patent number: 8391059Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.Type: GrantFiled: June 24, 2011Date of Patent: March 5, 2013Assignee: IMECInventors: Zhichao Lu, Nadine Collaert, Marc Aoulaiche, Malgorzata Jurczak
-
Patent number: 8319295Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.Type: GrantFiled: January 9, 2008Date of Patent: November 27, 2012Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Nadine Collaert, Paul Zimmerman, Marc Demand, Werner Boullart, Adelina K. Shickova
-
Publication number: 20110317486Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: IMECInventors: Zhichao Lu, Nadine Collaert, Marc Aoulaiche, Malgorzata Jurczak
-
Publication number: 20110068375Abstract: A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.Type: ApplicationFiled: November 19, 2010Publication date: March 24, 2011Applicant: IMECInventors: Stefan Jakschik, Nadine Collaert
-
Patent number: 7842559Abstract: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.Type: GrantFiled: December 19, 2008Date of Patent: November 30, 2010Assignee: IMECInventors: Stefan Jakschik, Nadine Collaert
-
Publication number: 20090159972Abstract: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.Type: ApplicationFiled: December 19, 2008Publication date: June 25, 2009Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC)Inventors: Stefan Jakschik, Nadine Collaert
-
Patent number: 7494902Abstract: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.Type: GrantFiled: June 22, 2007Date of Patent: February 24, 2009Assignee: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Malgorzata Jurczak, Rita Rooyackers, Nadine Collaert
-
Publication number: 20090020786Abstract: A method for forming a semiconductor device on a substrate having a first major surface lying in a plane and the semiconductor device are disclosed. In one aspect, the method comprises, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to a major surface of the substrate, forming locally modified regions at locations in the substrate not covered by the structure, thus locally increasing etching resistance of these regions. Forming locally modified regions may prevent under-etching of the structure during further process steps in the formation of the semiconductor device.Type: ApplicationFiled: June 24, 2008Publication date: January 22, 2009Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), STMicroelectronics (Crolles2) SASInventors: Damien Lenoble, Nadine Collaert