Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method according to the present disclosure is performed by an image decoding apparatus. The image decoding method may comprise deriving a prediction sample of a current block based on motion information of the current block, determining whether prediction refinement with optical flow (PROF) applies to the current block, deriving, based on that the PROF applies to the current block, a difference motion vector for each sample position in the current block, deriving a gradient for each sample position in the current block, deriving a PROF offset based on the difference motion vector and the gradient, and deriving a refined prediction sample for the current block based on the PROF offset.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method according to the present disclosure is performed by an image decoding apparatus. The image decoding method comprises deriving a prediction sample of a current block based on motion information of the current block, deriving a reference picture resampling (RPR) condition for the current block, determining whether prediction refinement with optical flow (PROF) applies to the current block based on the RPR condition, and deriving a refined prediction sample for the current block by applying PROF to the current block.

Abstract: A method for reducing surface defects of a semiconductor substrate comprising selectively etching an insulation film formed on a semiconductor substrate and forming a contact hole, forming a conductive layer in a contact hole and on the upper surface of the insulation film, performing a Chemical Mechanical Polishing process on the conductive layer to expose the upper surface of the insulation film and forming a conductive layer plug in the contact hole, forming an oxide film on the upper surface of the conductive plug, and washing the conductive layer plug and the surface of the insulation film. In order to reduce surface defects of a semiconductor substrate, an oxide film is formed on the surface of the semiconductor substrate during the Chemical Mechanical Polishing process or after the Chemical Mechanical Polishing process, so that the efficiency of the post-washing process is heightened and the surface defects of the substrate is reduced.

Abstract: The method of forming a plug of a semiconductor device includes sequentially forming a conductive film and an insulation film over a semiconductor substrate having a high density region and a low density region. The high density region has a greater number of structures formed thereover than the low density region. Next, a first CMP (chemical mechanical polishing) process, in which slurry for removing insulating film is used, is performed to selectively remove the insulating film and expose a top surface of the conductive film. Then a second CMP process, in which slurry for removing conductive film is used, is performed to selectively remove the conductive film and the insulating film and expose structures in the high density region.

Abstract: A method for reducing surface defects of a semiconductor substrate comprising selectively etching an insulation film formed on a semiconductor substrate and forming a contact hole, forming a conductive layer in a contact hole and on the upper surface of the insulation film, performing a Chemical Mechanical Polishing process on the conductive layer to expose the upper surface of the insulation film and forming a conductive layer plug in the contact hole, forming an oxide film on the upper surface of the conductive plug, and washing the conductive layer plug and the surface of the insulation film. In order to reduce surface defects of a semiconductor substrate, an oxide film is formed on the surface of the semiconductor substrate during the Chemical Mechanical Polishing process or after the Chemical Mechanical Polishing process, so that the efficiency of the post-washing process is heightened and the surface defects of the substrate is reduced.

Abstract: The method of forming a plug of a semiconductor device includes sequentially forming a conductive film and an insulation film over a semiconductor substrate having a high density region and a low density region. The high density region has a greater number of structures formed thereover than the low density region. Next, a first CMP (chemical mechanical polishing) process, in which slurry for removing insulating film is used, is performed to selectively remove the insulating film and expose a top surface of the conductive film. Then a second CMP process, in which slurry for removing conductive film is used, is performed to selectively remove the conductive film and the insulating film and expose structures in the high density region.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: A method for forming metal line of a semiconductor device in which, if the aspect ratio of the contact holes is big, contact holes are buried with a CVD method using the HDP method, and the line process is simplified to improve the reliability is disclosed, including the steps of forming an insulating film having a contact hole on a semiconductor substrate; forming a barrier metal layer on the insulating film including the contact hole; and forming a metal line layer on the barrier metal layer with a CVD method using a high density plasma.

Abstract: A method and apparatus for controlling the amount of ozone concentration in the layers of a film depositing system and the multi-layered structure produced thereby, whereby the concentration of ozone in each layer gradually changes from a low ozone concentration in the first deposited layer to a high ozone concentration in the last deposited layer.

Abstract: A method and apparatus for controlling the amount of ozone concentration in the layers of a film depositing system and the multi-layered structure produced thereby, whereby the concentration of ozone in each layer gradually changes from a low ozone concentration in the first deposited layer to a high ozone concentration in the last deposited layer.

Abstract: A method of forming an interconnection for a semiconductor device includes the steps of: forming a lower conductive line on a semiconductor substrate and forming a first insulating layer on the semiconductor substrate and the lower conductive line; patterning the first insulating layer to form a first insulating layer pattern which is narrower than the lower conductive line on the lower conductive line; forming a second insulating layer on an overall surface of the substrate and on the first insulating layer pattern, to planarize a surface of the second insulating layer; patterning the second insulating layer to expose a surface of the first insulating layer pattern and to form a first trench wider than the first insulating layer pattern on an upper portion of the first insulating pattern; removing the first insulating layer pattern, to thereby form a second trench at a lower portion of the first trench; and filling the first and second trenches with conductive material, to thereby form an upper conductive li

Abstract: A method for fabricating wiring in a semiconductor device in which a conductor line and a contact hole are formed by self-alignment, includes the steps of: forming an insulating layer on a substrate; forming an etch-step layer on the insulating layer; etching the etch-stop layer of a wiring region connected to a window and the insulating layer to a predetermined thickness; forming a mask layer on the etch-stop layer and the insulating layer; etching the mask layer to remove the mask layer at the central part of the window; and etching the insulating layer of the central part of the window so as to form a contact hole. By applying such a method, a highly improved reliability can be obtained, and a process thereof is simplified by a single photolithography. Also, the contact hole is formed by self-alignment in the lengthwise direction and in the vertical direction of the conductor line.

Abstract: A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, and selectively removing the polished conductive layer to form the interconnection pattern.

Abstract: A method for forming a Damascene structured multi-layered metal wiring for a semiconductor element, which includes the steps for forming a first insulating layer on the surface of a semiconductor substrate, forming a lower metal wiring pattern on the first insulating layer, forming a second insulating layer on the first insulating layer and the lower metal wiring pattern, forming contacts by subjecting the second insulating layer to etching, successively depositing first and second upper metals over the second insulating layer and the contact, subjecting the second upper metal to etching until the first upper metal is exposed, and forming an upper metal wiring pattern having a double metal structure by subjecting the first upper metal to etching until the second insulating layer is exposed. The upper wiring layer is preferably formed of aluminum deposited by a sputtering method and tungsten deposited by a chemical vapor deposition method.