Patents by Inventor Nae-In Lee

Nae-In Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190206794
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangho RHA, Jongmin BAEK, Wookyung YOU, Sanghoon AHN, Nae-In LEE
  • Publication number: 20190189744
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20190189540
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Tsukasa MATSUDA, Rak-Hwan KIM, Byung-Hee KIM, Nae-In LEE, Jong-Jin LEE
  • Patent number: 10304734
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Publication number: 20190149820
    Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 16, 2019
    Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaborati on Foundation, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Sung Chang LIM, Ha Hyun LEE, Se Yoon JEONG, Hui Yong KIM, Suk Hee CHO, Jong Ho KIM, Jin Ho LEE, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Dong Gyu SIM, Seoung Jun OH, Gwang Hoon PARK, Sea Nae PARK, Chan Woong JEON
  • Publication number: 20190139333
    Abstract: Provided is a method of determining a recording time of an event data recorder (EDR) includes obtaining, from the EDR of a vehicle, main engine revolutions per minute (RPM) record data of which the recording time is unknown; obtaining, from an acoustic storage apparatus, time domain acoustic data including acoustic information of an event time of the vehicle; calculating frequency domain acoustic data from the time domain acoustic data by using Fourier transformation; calculating RPM estimation data of the vehicle of the event time from the frequency domain acoustic data by using order analysis; and determining whether a time when the EDR records the RPM record data is identical to the event time by comparing the RPM estimation data of the vehicle with the RPM record data.
    Type: Application
    Filed: August 23, 2018
    Publication date: May 9, 2019
    Inventors: Jae Hyeong Lee, Young Nae Lee, Nam Kyu Park, Jong Chan Park, Jong Jin Park
  • Publication number: 20190137533
    Abstract: Provided is a method of estimating a speed of a vehicle includes obtaining time domain acoustic data from an acoustic storage apparatus when the vehicle passes over a horizontally grooved road; calculating frequency domain acoustic data from the time domain acoustic data by using Fourier transformation; calculating, from the frequency domain acoustic data, a resonance frequency of sound generated between tires of the vehicle and horizontal groovings in the road; and estimating the speed when the vehicle passes over the horizontally grooved road by multiplying the resonance frequency by an interval of the horizontal groovings.
    Type: Application
    Filed: August 23, 2018
    Publication date: May 9, 2019
    Inventors: Jae Hyeong Lee, Young Nae Lee, Nam Kyu Park, Jong Chan Park, Jong Jin Park
  • Patent number: 10276694
    Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 30, 2019
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Ha-Jin Lim, Hyeong-Joon Kim, Nae-In Lee
  • Patent number: 10269712
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 10217820
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20190023634
    Abstract: The present invention relates to a method for purifying phenol, which comprises: supplying a feed comprising phenol, acetone, hydroxyacetone and water to a distillation column at 60° C. to 95° C.; separating the feed into a first fraction, which comprises the acetone, and separates to the upper part of the distillation column and a second fraction, which comprises the phenol, and separates to the lower part of the distillation column; and recovering the first fraction and the second fraction, respectively.
    Type: Application
    Filed: November 10, 2017
    Publication date: January 24, 2019
    Inventors: Si Nae LEE, Sung Kyu LEE, Joon Ho SHIN
  • Publication number: 20190019759
    Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Inventors: Sang Hoon AHN, Tae Soo KIM, Jong Min BAEK, Woo Kyung YOU, Thomas OSZINDA, Byung Hee KIM, Nae In LEE
  • Patent number: 10181525
    Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghyun Roh, Pankwi Park, Dongsuk Shin, Chulwoong Lee, Nae-in Lee
  • Publication number: 20180366671
    Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.
    Type: Application
    Filed: January 13, 2018
    Publication date: December 20, 2018
    Inventors: Yi-Koan HONG, Kwang-Jin MOON, Nae-In LEE, Ho-Jin LEE
  • Patent number: 10153219
    Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-jun Jeon, Nae-in Lee, Byung-Iyul Park
  • Publication number: 20180330987
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: WOO KYUNG YOU, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
  • Patent number: 10128148
    Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Viet Ha Nguyen, Nae In Lee, Thomas Oszinda, Byung Hee Kim, Jong Min Baek, Tae Jin Yim
  • Publication number: 20180246196
    Abstract: Provided is a method of estimating velocity of a vehicle, in which at least one black box is installed, the method including: receiving acoustic information from the black box, the acoustic information being synchronized with time of a certain image; transforming the acoustic information of a time domain to frequency data of a frequency domain via fast Fourier transformation (FFT); calculating revolutions per minute (RPM) of a main engine from the frequency data by using order analysis; and calculating velocity of the vehicle at the time of the certain image by using the RPM of the main engine and vehicle information.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 30, 2018
    Inventors: Jae Hyeong Lee, Young Nae Lee, Nam Kyu Park, Jong Chan Park, Jong Jin Park
  • Patent number: 10062609
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Publication number: 20180218980
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Application
    Filed: March 21, 2018
    Publication date: August 2, 2018
    Inventors: Sangho Rha, Jongmin Beak, Wookyung You, Sanghoon Ahn, Nae-In Lee