Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.

Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material. The semiconductor layer structure includes a drift region of a first conductivity type and a plurality of fin structures protruding from the drift region. The fin structures comprise respective source regions of the first conductivity type and respective channel regions between the respective source regions and the drift region. Related devices and methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Power switching devices include a semiconductor layer structure, a unit cell transistor comprising a gate finger, the gate finger extending in a first direction in a gate trench that is below a surface of the semiconductor layer structure, and a gate bus, wherein a portion of the gate bus vertically overlaps the gate finger and is electrically connected to the gate finger.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.