Patents by Inventor Nae-In Lee

Nae-In Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973966
    Abstract: A video decoding method and a video decoding apparatus are configured to decode video. To efficiently code residual blocks obtained from block-based motion compensation, a video encoding apparatus and the video decoding apparatus divide a relevant residual block of a current block into two subblocks in a horizontal or vertical direction and encode one residual subblock alone out of the two residual subblocks.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: April 30, 2024
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Kwangwoon University Industry-Academic Collaboration Foundation
    Inventors: Dong Gyu Sim, Jong Seok Lee, Sea Nae Park, Seung Wook Park, Wha Pyeong Lim
  • Patent number: 11962775
    Abstract: An inverse quantization method is implemented by an inverse quantization device, the method configured for acquiring quantized coefficients, estimating a quantization parameter in quantization groups or quantization parameter prediction group units, generating an inverse quantization matrix for adaptive quantization, and generating transform coefficients from the quantized coefficients using the quantization parameter and the inverse quantization matrix.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: April 16, 2024
    Assignees: Hyundai Motor Company, Kia Corporation, Kwangwoon University Industry-Academic Collaboration Foundation
    Inventors: Dong Gyu Sim, Sea Nae Park, Jong Seok Lee, Seung Wook Park, Wha Pyeong Lim
  • Patent number: 11962776
    Abstract: An inverse quantization method is implemented by an inverse quantization device, the method configured for acquiring quantized coefficients, estimating a quantization parameter in quantization groups or quantization parameter prediction group units, generating an inverse quantization matrix for adaptive quantization, and generating transform coefficients from the quantized coefficients using the quantization parameter and the inverse quantization matrix.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: April 16, 2024
    Assignees: Hyundai Motor Company, Kia Corporation, Kwangwon University Industry-Academic Collaboration Foundation
    Inventors: Dong Gyu Sim, Sea Nae Park, Jong Seok Lee, Seung Wook Park, Wha Pyeong Lim
  • Patent number: 11962777
    Abstract: An inverse quantization method is implemented by an inverse quantization device, the method configured for acquiring quantized coefficients, estimating a quantization parameter in quantization groups or quantization parameter prediction group units, generating an inverse quantization matrix for adaptive quantization, and generating transform coefficients from the quantized coefficients using the quantization parameter and the inverse quantization matrix.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: April 16, 2024
    Assignees: Hyundai Motor Company, Kia Corporation, Kwangwoon University Industry-Academic Collaboration Foundation
    Inventors: Dong Gyu Sim, Sea Nae Park, Jong Seok Lee, Seung Wook Park, Wha Pyeong Lim
  • Patent number: 11943441
    Abstract: An inverse quantization method is implemented by an inverse quantization device, the method configured for acquiring quantized coefficients, estimating a quantization parameter in quantization groups or quantization parameter prediction group units, generating an inverse quantization matrix for adaptive quantization, and generating transform coefficients from the quantized coefficients using the quantization parameter and the inverse quantization matrix.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: March 26, 2024
    Assignees: Hyundai Motor Company, Kia Corporation, Kwangwoon University Industry-Academic Collaboration Foundation
    Inventors: Dong Gyu Sim, Sea Nae Park, Jong Seok Lee, Seung Wook Park, Wha Pyeong Lim
  • Publication number: 20240073416
    Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, Universily-lndustry Cooperation Group of Kyung Hee University
    Inventors: Sung Chang LIM, Ha Hyun LEE, Se Yoon JEONG, Hui Yong KIM, Suk Hee CHO, Jong Ho KIM, Jin Ho LEE, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Dong Gyu SIM, Seoung Jun OH, Gwang Hoon PARK, Sea Nae PARK, Chan Woong JEON
  • Patent number: 11798906
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-Jin Lee
  • Publication number: 20220108962
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi JIN, Nae-in LEE, Jum-yong PARK, Jin-ho CHUN, Seong-min SON, Ho-Jin LEE
  • Patent number: 11251144
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
  • Patent number: 10978655
    Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 13, 2021
    Inventors: Yi-Koan Hong, Kwang-Jin Moon, Nae-In Lee, Ho-Jin Lee
  • Patent number: 10867923
    Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hoon Ahn, Tae Soo Kim, Jong Min Baek, Woo Kyung You, Thomas Oszinda, Byung Hee Kim, Nae In Lee
  • Patent number: 10816567
    Abstract: Provided is a method of estimating a speed of a vehicle includes obtaining time domain acoustic data from an acoustic storage apparatus when the vehicle passes over a horizontally grooved road; calculating frequency domain acoustic data from the time domain acoustic data by using Fourier transformation; calculating, from the frequency domain acoustic data, a resonance frequency of sound generated between tires of the vehicle and horizontal groovings in the road; and estimating the speed when the vehicle passes over the horizontally grooved road by multiplying the resonance frequency by an interval of the horizontal groovings.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 27, 2020
    Assignee: Republic of Korea (National Forensic Service Director Ministry of Public Administration and Security)
    Inventors: Jae Hyeong Lee, Young Nae Lee, Nam Kyu Park, Jong Chan Park, Jong Jin Park
  • Patent number: 10770447
    Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
  • Patent number: 10734309
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Tsukasa Matsuda, Rak-Hwan Kim, Byung-Hee Kim, Nae-In Lee, Jong-Jin Lee
  • Patent number: 10707164
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 10700164
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20200066666
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
  • Patent number: 10556191
    Abstract: By using the distillation device of the present application, energy loss occurring in a purification process of a solution including a waste stripper and a stripped photoresist resin used in a stripping process of a photoresist can be minimized and the installation cost of the distillation device can be reduced compared to the case in which dual distillation columns are used, thereby increasing the economic feasibility of a process.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 11, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Si Nae Lee, Sung Kyu Lee, Sang Beom Lee, Sung Ho Lee, Jeong Seok Kim, Joon Ho Shin, Dae Chul Jung, Yong Hee Jang, Tae Moon Park, Hyun Jik Yi
  • Patent number: 10532968
    Abstract: The present invention relates to a method for purifying phenol, which comprises: supplying a feed comprising phenol, acetone, hydroxyacetone and water to a distillation column at 60° C. to 95° C.; separating the feed into a first fraction, which comprises the acetone, and separates to the upper part of the distillation column and a second fraction, which comprises the phenol, and separates to the lower part of the distillation column; and recovering the first fraction and the second fraction, respectively.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 14, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Si Nae Lee, Sung Kyu Lee, Joon Ho Shin
  • Publication number: 20200006269
    Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.
    Type: Application
    Filed: September 5, 2019
    Publication date: January 2, 2020
    Inventors: Yi-Koan HONG, Kwang-Jin MOON, Nae-In LEE, Ho-Jin LEE