Patents by Inventor Naewon Lee

Naewon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105886
    Abstract: A display apparatus comprises: a light source device configured to emit light; a display panel configured to display the light emitted from the light source device; and an optical sheet disposed at a rear of the display panel, wherein the light source device may include: a substrate; at least one light source electrically connected to the substrate; a light conversion member configured to convert a wavelength of light emitted from the light source; and a conversion member cover covering the light conversion member and configured to allow light to pass therethrough.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeongshan NA, Youngchol LEE, Naewon JANG, Dukjin JEON
  • Patent number: 7374967
    Abstract: In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 20, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Naewon Lee
  • Patent number: 7112473
    Abstract: In a double side stack packaging a plurality of chips, a hole is formed in a substrate. A first chip is attached to a bottom surface of the substrate by using a thermo compression and is electrically interconnected to terminals formed at sidewall of the hole using a wire bonding. Next, an epoxy is coated on the substrate and the first chip and a first heat spreader is installed thereon and then the epoxy is cured. Thereafter, a second chip is attached to a top surface of the substrate by using the epoxy and is electrically interconnected to terminals formed on the substrate using the wire bonding. And then, an encapsulation resin is coated on the substrate and the first chip and a second heat spreader is installed thereon and then the epoxy is cured.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: September 26, 2006
    Assignee: Dongbuanam Semiconductor Inc.
    Inventor: Naewon Lee
  • Publication number: 20040152235
    Abstract: In a double side stack packaging a plurality of chips, a hole is formed in a substrate. A first chip is attached to a bottom surface of the substrate by using a thermo compression and is electrically interconnected to terminals formed at sidewall of the hole using a wire bonding. Next, an epoxy is coated on the substrate and the first chip and a first heat spreader is installed thereon and then the epoxy is cured. Thereafter, a second chip is attached to a top surface of the substrate by using the epoxy and is electrically interconnected to terminals formed on the substrate using the wire bonding. And then, an encapsulation resin is coated on the substrate and the first chip and a second heat spreader is installed thereon and then the epoxy is cured.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicant: Dongbu Electronics Co., Ltd.
    Inventor: Naewon Lee
  • Publication number: 20040150098
    Abstract: In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicant: Dongbu Electronics Co., Ltd.
    Inventor: Naewon Lee