Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.

Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.

Abstract: Interconnect structures are disclosed. An example includes conductive traces over a first dielectric layer, dielectric helmet structures over top surfaces of the conductive traces, and a second dielectric layer over the helmet structures. Spaces between adjacent ones of conductive traces are devoid of material. A bottom surface of the second dielectric layer is between top surfaces of the dielectric structures and bottom surfaces of the helmet structures, or co-planar with the top surface of the helmet structures, but the airgap extends above tops of the conductive traces. Another example includes a dielectric adjacent to upper sections but not lower sections of conductive traces, so as to provide airgaps between adjacent lower sections. Alternatively, a first dielectric material is adjacent the upper sections and a second compositionally different dielectric material is adjacent the lower sections. In either case, the sidewalls of the upper sections of the interconnect features may include scalloping.

Abstract: Interconnect structures are disclosed. An example includes conductive traces over a first dielectric layer, dielectric helmet structures over top surfaces of the conductive traces, and a second dielectric layer over the helmet structures. Spaces between adjacent ones of conductive traces are devoid of material. A bottom surface of the second dielectric layer is between top surfaces of the dielectric structures and bottom surfaces of the helmet structures, or co-planar with the top surface of the helmet structures, but the airgap extends above tops of the conductive traces. Another example includes a dielectric adjacent to upper sections but not lower sections of conductive traces, so as to provide airgaps between adjacent lower sections. Alternatively, a first dielectric material is adjacent the upper sections and a second compositionally different dielectric material is adjacent the lower sections. In either case, the sidewalls of the upper sections of the interconnect features may include scalloping.