Patents by Inventor Naftall E. Lustig

Naftall E. Lustig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6914320
    Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: July 5, 2005
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
  • Patent number: 6887783
    Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: May 3, 2005
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
  • Publication number: 20040173907
    Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
    Type: Application
    Filed: March 23, 2004
    Publication date: September 9, 2004
    Inventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
  • Publication number: 20040115873
    Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
    Type: Application
    Filed: August 28, 2003
    Publication date: June 17, 2004
    Inventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
  • Patent number: 6251787
    Abstract: Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Wilma J. Horkans, Stephen E. Luce, Naftall E. Lustig, Keith R. Pope, Peter D. Roper