Patents by Inventor Nag Yong CHOI

Nag Yong CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240188293
    Abstract: A semiconductor memory device including a substrate; a mold structure including gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate, intersecting the gate electrodes, and passing through the mold structure; cell contacts connected to the gate electrodes; a first interlayer insulating layer on the mold structure and covering the channel structures and cell contacts; first metal patterns connected to the channel structures, an upper surface of the first metal patterns being coplanar with an upper surface of the first interlayer insulating layer; second metal patterns connected to the cell contacts, an upper surface of the second metal patterns being coplanar with the upper surface of the first metal patterns; a first blocking layer along the upper surface of the first interlayer insulating layer, the first metal patterns, and the second metal patterns; and a first dummy vias passing through the first blocking layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: June 6, 2024
    Inventors: Sam Ki KIM, Nam Bin KIM, Ji Woong KIM, Tae Hun KIM, Ki Bong MOON, Sae Rom LEE, Sung-Bok LEE, Jun Hee LIM, Nag Yong CHOI, Sun Gyung HWANG
  • Publication number: 20240188294
    Abstract: A semiconductor memory device comprising a substrate including a cell array area and an extension area, a mold structure including, a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate, and a plurality of mold insulating films stacked alternately with the plurality of gate electrodes, a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes, a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes, a first interlayer insulating film on the mold structure so as to cover the plurality of channel structures and the plurality of cell contacts.
    Type: Application
    Filed: August 11, 2023
    Publication date: June 6, 2024
    Inventors: Sam Ki KIM, Nam Bin KIM, Ji Woong KIM, Tae Hun KIM, Sae Rom LEE, Jun Hee LIM, Nag Yong CHOI, Sun Gyung HWANG
  • Patent number: 9837165
    Abstract: A data storage device includes a semiconductor structure including a first conductive-type region having a first-type conductivity, a second conductive-type region spaced apart from the first conductive-type region and having a second-type conductivity opposite to the first-type conductivity, and a semiconductor region between the first conductive-type region and the second conductive-type region and including a neighboring portion adjacent to the second conductive-type region; a mode select transistor including a gate electrode aligned with the neighboring portion and an insulation layer between the gate electrode and the neighboring portion; a plurality of memory cell transistors including a plurality of control gate electrodes aligned with the semiconductor region, and a data storage layer interposed between the plurality of control gate electrodes and the semiconductor region; a first wire electrically connected to the first conductive-type region; and a second wire including an ambipolar contact having a
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 5, 2017
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong Ho Lee, Nag Yong Choi
  • Patent number: 9734913
    Abstract: A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 15, 2017
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong Ho Lee, Ho Jung Kang, Nag Yong Choi, Byeong Il Han, Kyoung Jin Park, Sung Yong Chung
  • Publication number: 20170194057
    Abstract: A data storage device includes a semiconductor structure including a first conductive-type region having a first-type conductivity, a second conductive-type region spaced apart from the first conductive-type region and having a second-type conductivity opposite to the first-type conductivity, and a semiconductor region between the first conductive-type region and the second conductive-type region and including a neighbouring portion adjacent to the second conductive-type region; a mode select transistor including a gate electrode aligned with the neighbouring portion and an insulation layer between the gate electrode and the neighbouring portion; a plurality of memory cell transistors including a plurality of control gate electrodes aligned with the semiconductor region, and a data storage layer interposed between the plurality of control gate electrodes and the semiconductor region; a first wire electrically connected to the first conductive-type region; and a second wire including an ambipolar contact havin
    Type: Application
    Filed: December 29, 2016
    Publication date: July 6, 2017
    Inventors: Jong Ho LEE, Nag Yong CHOI
  • Publication number: 20160260490
    Abstract: A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 8, 2016
    Inventors: Jong Ho LEE, Ho Jung KANG, Nag Yong CHOI, Byeong Il HAN, Kyoung Jin PARK, Sung Yong CHUNG