Patents by Inventor Naga Chandrasekaran

Naga Chandrasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923991
    Abstract: Certain aspects of the present disclosure provide techniques for dynamic configuration of demodulation reference signals (DMRSs). A method that may be performed by a base station (BS) includes receiving one or more uplink signals from at least one user equipment (UE); estimating a Doppler shift associated with the one or more uplink signals; determining a density of reference signals (RSs) within a slot for the at least one UE based, at least in part, on the estimated Doppler shift associated with the one or more uplink signals; and transmitting information to the at least one UE indicating an allocation of RS resources for the UE, wherein the allocation of the RS resources is based on the density of the RSs for the at least one UE.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Satish Kumar, Siva Naga Raju Undrakunta, Harika Lavanuru, Sarath Pinayour Chandrasekaran, Loksiva Paruchuri, Ashok Kumar Tripathi, Raja Sekhar Bachu
  • Patent number: 8727835
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20140024297
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Patent number: 8550878
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20120225612
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Application
    Filed: May 11, 2012
    Publication date: September 6, 2012
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20120223277
    Abstract: Methods for orienting a plurality of sliver structures include applying at least one directional force to a group of sliver structures each having an orientation material applied to an edge to cause the plurality of sliver structures to orient in a common direction. The method may also include capturing the oriented sliver structures in a capture device to maintain the orientation of the sliver structures in the common direction. The oriented sliver structures may be used to form sub-assemblies such as solar array sub-assemblies that are used to generate solar power. Methods of applying an orientation material to sliver structures and resulting sliver structures are also disclosed.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Naga Chandrasekaran
  • Publication number: 20120222720
    Abstract: A solar panel assembly may comprise a support member, a plurality of elongate solar cells, at least one motive member, and at least one actuator. Each elongate solar cell of the plurality may be pivotally coupled to the support member at a first location on each elongate solar cell, and each motive member may be pivotally coupled to each elongate solar cell of the plurality of elongate solar cells at a second location on each elongate solar cell, the second location offset a distance from the first location. Additionally, each actuator may be operably coupled to the at least one motive member. A method of operating a solar panel assembly may comprise rotating each of a plurality of elongate solar cells within the solar panel assembly relative to each other of the plurality of elongate solar cells within the solar panel assembly.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Naga Chandrasekaran, Gurtej S. Sandhu
  • Publication number: 20120222717
    Abstract: A method of assembling elongate solar cells into an assembly may comprise forming a unitary structure comprising a plurality of elongate solar cell precursor structures from a semiconductor wafer and attaching an adhesive surface of a transfer structure to an edge of each of the plurality of elongate solar cell precursor structures. The method may further comprise attaching the plurality of elongate solar cells to an expandable fixture and expanding the expandable fixture to change at least one of an orientation and a position of the plurality of elongate solar cells relative to one another. Additionally, a solar panel assembly may comprise a plurality of elongate solar cells positioned on a substrate, major surfaces of the plurality of elongate solar cells oriented in a non-planar configuration. Furthermore, elongate solar cells may comprise non-linear shapes in an as-formed state. Transfer structures and expandable fixtures useful in performing methods of the disclosure are also described.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Naga Chandrasekaran, Gurtej S. Sandhu
  • Patent number: 8227875
    Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer, Naga Chandrasekaran
  • Patent number: 8192257
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20110269305
    Abstract: An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Inventor: Naga Chandrasekaran
  • Patent number: 7998809
    Abstract: An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: August 16, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Naga Chandrasekaran
  • Publication number: 20100244158
    Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.
    Type: Application
    Filed: June 9, 2010
    Publication date: September 30, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Yongjun Jeff Hu, Allen McTeer, Naga Chandrasekaran
  • Patent number: 7749849
    Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: July 6, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer, Naga Chandrasekaran
  • Publication number: 20090152629
    Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Yongjun Jeff Hu, Allen McTeer, Naga Chandrasekaran
  • Patent number: 7452816
    Abstract: This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical polishing. In one implementation, the organic material is chemical mechanically polished using a polishing pad downforce on the substrate of less than or equal to 1.75 psi, using an aqueous slurry comprising abrasive particles comprising an individual particle size of less than or equal to 100 nanometers and at a particle concentration of less than or equal to 20% by weight, and at least one of an acid or a surfactant effective to achieve a removal rate of the organic material of at least 500 Angstroms per minute. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: November 18, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Naga Chandrasekaran, Andrew Carswell
  • Publication number: 20080026525
    Abstract: This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical polishing. In one implementation, the organic material is chemical mechanically polished using a polishing pad downforce on the substrate of less than or equal to 1.75 psi, using an aqueous slurry comprising abrasive particles comprising an individual particle size of less than or equal to 100 nanometers and at a particle concentration of less than or equal to 20% by weight, and at least one of an acid or a surfactant effective to achieve a removal rate of the organic material of at least 500 Angstroms per minute. Other aspects and implementations are contemplated.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Zhenyu Lu, Naga Chandrasekaran, Andrew Carswell
  • Publication number: 20070264777
    Abstract: An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 15, 2007
    Inventor: Naga Chandrasekaran
  • Publication number: 20070238297
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 11, 2007
    Applicant: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan