Patents by Inventor NAGA P. GORTI
NAGA P. GORTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960893Abstract: A method, programming product, and/or system for prefetching instructions includes an instruction prefetch table that has a plurality of entries, each entry for storing a first portion of an indirect branch instruction address and a target address, wherein the indirect branch instruction has multiple target addresses and the instruction prefetch table is accessed by an index obtained by hashing a second portion of bits of the indirect branch instruction address with an information vector of the indirect branch instruction. A further embodiment includes a first prefetch table for uni-target branch instructions and a second prefetch table for multi-target branch instructions. In operation it is determined whether a branch instruction hits in one of the multiple prefetch tables; a target address for the branch instruction is read from the respective prefetch table in which the branch instruction hit; and the branch instruction is prefetched to an instruction cache.Type: GrantFiled: December 29, 2021Date of Patent: April 16, 2024Assignee: International Business Machines CorporationInventors: Naga P. Gorti, Mohit Karve
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Patent number: 11947461Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.Type: GrantFiled: January 10, 2022Date of Patent: April 2, 2024Assignee: International Business Machines CorporationInventors: Mohit Karve, Naga P. Gorti, Guy L. Guthrie, Sanjeev Ghai
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Patent number: 11847458Abstract: Methods and systems for determining a priority of a threads is described. A processor can execute branch instructions of the thread. The processor can predict branch instruction outcomes of the branch instructions of the thread. The processor can increment a misprediction count of the thread in response to an actual execution of a branch instruction of the thread being different from a corresponding branch instruction prediction outcome of the thread. The processor can determine the priority of the thread based on the misprediction count of the thread.Type: GrantFiled: July 2, 2021Date of Patent: December 19, 2023Assignee: International Business Machines CorporationInventors: Richard J. Eickemeyer, Ehsan Fatehi, John B. Griswell, Jr., Naga P. Gorti
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Patent number: 11822922Abstract: A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.Type: GrantFiled: December 31, 2021Date of Patent: November 21, 2023Assignee: International Business Machines CorporationInventors: Mohit Karve, Naga P. Gorti
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Patent number: 11816034Abstract: A Bloom filter is used to track contents of a cache. A system checks the Bloom filter before deciding whether to prefetch an address (by hashing the address and checking a value of the Bloom filter at an index based on the hash). This allows the system to utilize more aggressive prefetching schemes by reducing the risk of wasteful redundant prefetch operations.Type: GrantFiled: October 26, 2020Date of Patent: November 14, 2023Assignee: International Business Machines CorporationInventors: Mohit Karve, Naga P. Gorti
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Publication number: 20230222066Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.Type: ApplicationFiled: January 10, 2022Publication date: July 13, 2023Inventors: Mohit Karve, Naga P. Gorti, Guy L. Guthrie, Sanjeev Ghai
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Publication number: 20230214221Abstract: A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.Type: ApplicationFiled: December 31, 2021Publication date: July 6, 2023Inventors: Mohit Karve, Naga P. Gorti
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Publication number: 20230205543Abstract: A method, programming product, and/or system for prefetching instructions includes an instruction prefetch table that has a plurality of entries, each entry for storing a first portion of an indirect branch instruction address and a target address, wherein the indirect branch instruction has multiple target addresses and the instruction prefetch table is accessed by an index obtained by hashing a second portion of bits of the indirect branch instruction address with an information vector of the indirect branch instruction. A further embodiment includes a first prefetch table for uni-target branch instructions and a second prefetch table for multi-target branch instructions. In operation it is determined whether a branch instruction hits in one of the multiple prefetch tables; a target address for the branch instruction is read from the respective prefetch table in which the branch instruction hit; and the branch instruction is prefetched to an instruction cache.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Inventors: Naga P. Gorti, Mohit Karve
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Patent number: 11586440Abstract: A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.Type: GrantFiled: June 1, 2021Date of Patent: February 21, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naga P. Gorti, Mohit Karve
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Patent number: 11561796Abstract: A computer-implemented method to prefetch non-sequential instruction addresses (I/A) includes, determining, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's. The method further includes storing the first I/A in a linked miss-to-miss (LMTM) table. The method also includes determining a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's. The method includes linking, in the LMTM table, the second miss to the first miss. The method also includes prefetching, in response to a third access attempt of the first I/A, the second I/A in the cache.Type: GrantFiled: July 15, 2020Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Naga P. Gorti, Mohit Karve
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Publication number: 20230004394Abstract: Methods and systems for determining a priority of a threads is described. A processor can execute branch instructions of the thread. The processor can predict branch instruction outcomes of the branch instructions of the thread. The processor can increment a misprediction count of the thread in response to an actual execution of a branch instruction of the thread being different from a corresponding branch instruction prediction outcome of the thread. The processor can determine the priority of the thread based on the misprediction count of the thread.Type: ApplicationFiled: July 2, 2021Publication date: January 5, 2023Inventors: Richard J. Eickemeyer, Ehsan Fatehi, John B. Griswell, JR., Naga P. Gorti
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Patent number: 11526360Abstract: A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction prediction outcome, and the branch prediction unit. The branch predictor is turned off to save power and avoid miss-predictions when the branch predictor and/or branch prediction unit accuracy is lower than expected.Type: GrantFiled: November 20, 2018Date of Patent: December 13, 2022Assignee: International Business Machines CorporationInventors: Naga P. Gorti, Dave S. Levitan
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Publication number: 20220382552Abstract: A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.Type: ApplicationFiled: June 1, 2021Publication date: December 1, 2022Inventors: Naga P. Gorti, Mohit Karve
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Patent number: 11416257Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.Type: GrantFiled: April 10, 2019Date of Patent: August 16, 2022Assignee: International Business Machines CorporationInventors: Naga P. Gorti, Ehsan Fatehi, Nicholas R. Orzol, Christian Zoellin, Edmund J. Gieske
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Publication number: 20220129385Abstract: A Bloom filter is used to track contents of a cache. A system checks the Bloom filter before deciding whether to prefetch an address (by hashing the address and checking a value of the Bloom filter at an index based on the hash). This allows the system to utilize more aggressive prefetching schemes by reducing the risk of wasteful redundant prefetch operations.Type: ApplicationFiled: October 26, 2020Publication date: April 28, 2022Inventors: Mohit Karve, Naga P. Gorti
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Publication number: 20220019440Abstract: A computer-implemented method to prefetch non-sequential instruction addresses (I/A) includes, determining, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's. The method further includes storing the first I/A in a linked miss-to-miss (LMTM) table. The method also includes determining a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's. The method includes linking, in the LMTM table, the second miss to the first miss. The method also includes prefetching, in response to a third access attempt of the first I/A, the second I/A in the cache.Type: ApplicationFiled: July 15, 2020Publication date: January 20, 2022Inventors: Naga P. Gorti, Mohit Karve
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Patent number: 11194575Abstract: Provided is a method, computer program product, and system for performing data address prediction. The method comprises receiving a first instruction for execution by a processor. A load address predictor (LAP) accesses a LAP table entry for a section of an instruction cache. The section is associated with a plurality of instructions that includes the first instruction. The LAP predicts a set of data addresses that will be loaded using the LAP table entry. The method further comprises sending a recommendation to prefetch the set of data addresses to a load-store unit (LSU).Type: GrantFiled: November 7, 2019Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Mohit Karve, Naga P. Gorti, Edmund Joseph Gieske
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Patent number: 11182161Abstract: An information handling system includes a memory subsystem; a processor; and a link connecting the processor and memory subsystem, the processor having a memory controller to manage load instructions; a data cache to hold data for use by the processor; a load store unit to execute load instructions; an instruction fetch unit to fetch load instructions and a cache line utility tracker (CUT) table having a plurality of entries, each entry having a utility field to indicate the portions of a cache line of the load instruction that were used by the processor. The system configured to: determine whether the load instruction is in the CUT Table and in response determine from the CUT Table whether to request a partial cache line; and in response to the data not being in the data cache, transmit a memory request for a partial cache line.Type: GrantFiled: April 15, 2020Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Mohit Karve, Edmund Joseph Gieske, Naga P. Gorti
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Publication number: 20210326138Abstract: An information handling system includes a memory subsystem; a processor; and a link connecting the processor and memory subsystem, the processor having a memory controller to manage load instructions; a data cache to hold data for use by the processor; a load store unit to execute load instructions; an instruction fetch unit to fetch load instructions and a cache line utility tracker (CUT) table having a plurality of entries, each entry having a utility field to indicate the portions of a cache line of the load instruction that were used by the processor. The system configured to: determine whether the load instruction is in the CUT Table and in response determine from the CUT Table whether to request a partial cache line; and in response to the data not being in the data cache, transmit a memory request for a partial cache line.Type: ApplicationFiled: April 15, 2020Publication date: October 21, 2021Inventors: Mohit Karve, Edmund Joseph Gieske, Naga P. Gorti
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Patent number: 11151054Abstract: A central processing unit (CPU) sets a cache lookup operation to a first mode in which the CPU searches a cache and only performs an address translation in response to a cache miss. The CPU performs the cache lookup operation while in the first mode using an address that results in a cache miss. Responsive to the CPU detecting the cache miss, the CPU sets the cache lookup operation from the first mode to a second mode in which the CPU concurrently searches the cache and performs an address translation. The CPU performs a cache lookup operation while in the second mode using a second address that results in a cache hit. Responsive to detecting the cache hit, the CPU sets the cache lookup operation from the second mode to the first mode. This process repeats in cycles upon detection of cache hits and misses.Type: GrantFiled: June 27, 2019Date of Patent: October 19, 2021Assignee: International Business Machines CorporationInventors: Naga P. Gorti, Mohit Karve