Patents by Inventor NAGADASTAGIRI REDDY C

NAGADASTAGIRI REDDY C has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210358135
    Abstract: An example apparatus for tracking features in image data includes an image data receiver to receive initial image data corresponding to an image from a camera and store the image data a circular buffer. The apparatus also includes a feature detector to detect features in the image data. The apparatus further includes a feature sorter to sort the detected features to generate sorted feature points. The apparatus includes a feature tracker to track the sorted feature points in subsequent image data corresponding to the image received at the image data receiver. The subsequent image data is to replace the initial image data in the circular buffer.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Dipan Kumar Mandal, Nagadastagiri Reddy C, Mahesh Mamidipaka, Om J Omer
  • Patent number: 11080864
    Abstract: An example apparatus for tracking features in image data includes an image data receiver to receive initial image data corresponding to an image from a camera and store the image data a circular buffer. The apparatus also includes a feature detector to detect features in the image data. The apparatus further includes a feature sorter to sort the detected features to generate sorted feature points. The apparatus includes a feature tracker to track the sorted feature points in subsequent image data corresponding to the image received at the image data receiver. The subsequent image data is to replace the initial image data in the circular buffer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Dipan Kumar Mandal, Nagadastagiri Reddy C, Mahesh Mamidipaka, Om J Omer
  • Patent number: 10402413
    Abstract: A processor may include a plurality of processing elements and a hardware accelerator for selecting data elements. The hardware accelerator may: access an input data set comprising a set of data elements, each data element having a score value; increment bin counters based on the score values of the set of data elements, each bin counter to count a number of data elements with an associated score value; determine a cumulative sum of count values for a sequence of bin counters, the sequence beginning with a first bin counter of the plurality of bin counters; identify a second bin counter in the sequence of bin counters at which the cumulative sum reaches a selection quantity N; and generate an output data set based on a comparison of the set of data elements to a threshold score associated with the second bin counter.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Mahesh Mamidipaka, Srivatsava Jandhyala, Anish N K, Nagadastagiri Reddy C, Sreenivas Subramoney
  • Publication number: 20190043204
    Abstract: An example apparatus for tracking features in image data includes an image data receiver to receive initial image data corresponding to an image from a camera and store the image data a circular buffer. The apparatus also includes a feature detector to detect features in the image data. The apparatus further includes a feature sorter to sort the detected features to generate sorted feature points. The apparatus includes a feature tracker to track the sorted feature points in subsequent image data corresponding to the image received at the image data receiver. The subsequent image data is to replace the initial image data in the circular buffer.
    Type: Application
    Filed: January 8, 2018
    Publication date: February 7, 2019
    Applicant: Intel IP Corporation
    Inventors: Dipan Kumar Mandal, Nagadastagiri Reddy C., Mahesh Mamidipaka, Om J. Omer
  • Publication number: 20180285364
    Abstract: A processor may include a plurality of processing elements and a hardware accelerator for selecting data elements. The hardware accelerator may: access an input data set comprising a set of data elements, each data element having a score value; increment bin counters based on the score values of the set of data elements, each bin counter to count a number of data elements with an associated score value; determine a cumulative sum of count values for a sequence of bin counters, the sequence beginning with a first bin counter of the plurality of bin counters; identify a second bin counter in the sequence of bin counters at which the cumulative sum reaches a selection quantity N; and generate an output data set based on a comparison of the set of data elements to a threshold score associated with the second bin counter.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: MAHESH MAMIDIPAKA, SRIVATSAVA JANDHYALA, ANISH N K, NAGADASTAGIRI REDDY C, SREENIVAS SUBRAMONEY