Patents by Inventor Nagalinga Swamy B. Aremallapur

Nagalinga Swamy B. Aremallapur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transition fault test (TFT) clock receiver system
    Patent number: 11204385
    Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gautam Sanjay Kale, Nagalinga Swamy B. Aremallapur, Sundarrajan Rangachari
  • TRANSITION FAULT TEST (TFT) CLOCK RECEIVER SYSTEM
    Publication number: 20210148974
    Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.
    Type: Application
    Filed: April 30, 2020
    Publication date: May 20, 2021
    Inventors: Gautam Sanjy Kale, Nagalinga Swamy B. Aremallapur, Sundarrajan Rangachari